• Journal of Computing Science and Engineering
• /
• v.3 no.3
• /
• pp.181-194
• /
• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• Journal of Mechanical Science and Technology
• /
• v.19 no.7
• /
• pp.1460-1468
• /
• 2005

Two possible shape memory processes, austenite to detwinned martensite transformation and twinned martensite to detwinned martensite transformation of a shape memory alloy have been modeled and examined. Eshelby's equivalent inclusion method with Mori-Tanaka's mean field theory is used for modeling of the shape memory processes of TiNi shape memory alloy reinforced aluminum matrix composite. The shape memory amount of shape memory alloy, plastic strain and residual stress in the matrix are computed and compared for the two processes. It is shown that the shape memory amount shows differences in a small prestrain region, but the plastic strain and the residual stress in the matrix show differences in the whole prestrain region. The shape memory process with initially martensitic state of the shape memory alloy would be favorable to the increase in the yield stress of the composite owing to the large compressive residual stress and plastic strain in the matrix.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2003.09a
• /
• pp.652-655
• /
• 2003

The human being receives a new information from outside and the information shows gradual oblivion with time. But it remains in memory and isn't forgotten for a long time if the information is read several times over. For example, we assume that we memorize a telephone number when we listen and never remind we may forget it soon, but we commit to memory long time by repeating. If the human being received new information with strong stimulus, it could remain in memory without recalling repeatedly. The moments of almost losing one's life in on accident or getting a stroke of luck are rarely forgiven. The human being can keep memory for a long time in spite of the limit of memory for the mechanism mentioned above. In this paper, we will make a model explaining that mechanism using a neural network Adaptive Resonance Theory.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.3
• /
• pp.195-203
• /
• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.11a
• /
• pp.204-206
• /
• 2012

SMP(Symmetric Multi-Processing)는 Shared memory bus 를 사용함으로써 scalability 가 제한적이었다. 이런 SMP의 scalability 제한을 극복하기 위해 제안 된 것이 NUMA(Non Uniform Memory Access)이다. NUMA는 memory bus 를 CPU 별 local 하게 가지고 있어 자신이 가지는 memory 영역에 대해서는 다른 영역을 접근하는 것 보다 더 빠른 latency 를 가지는 구조이다. Local 한 memory 영역의 존재는 scalability를 높여 주었지만 서버 가상화 환경에서 VM을 동적으로 scheduling 을 하였을 때 VM의 page 가 실행되는 core 의 local 한 메모리 영역에 존재하지 않게 되면 remote access로 인해 local access보다 성능이 떨어진다. 이 논문에서는 서버 가상화 환경에서 최신 architecture인 AMD bulldozer에서 NUMA affinity가 위반되었을 때 발생하는 성능 저하와 어떤 상황에서 이런 NUMA affinity가 위반되어도 성능저하가 없는지 연구하였다.

• Journal of the Korea Convergence Society
• /
• v.8 no.11
• /
• pp.353-361
• /
• 2017

The purpose of this study is to provide basic data to confirm the necessity and effectiveness of the memory school by investigating the perception of users and caregivers about the services and programs provided by the memory school, a social welfare institution for the elderly with minor dementia. For this purpose, 363 students and students in Daegu City were surveyed about the satisfaction and attitude of using memory school. As a result of the analysis, it was found that the use of the memory school is very helpful to the users, and at the same time, it is very meaningful for the decrease of the caregiver burden of the caregiver. Thus, it can be seen that the memory school has the effect of appropriately matching the installation purpose of the facility. In particular, it was found that the degree of satisfaction with the program level, type of service, and future sustainability of the memory school exceeded 90%. Therefore, this study aims to provide policy implications for the social welfare response for the elderly with mild dementia and for the basic data on the memory school for this purpose.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.49 no.7
• /
• pp.71-79
• /
• 2012

As advances in computer technology, dissemination of smartphones and tablet PCs has increased and digital media has become easily accessible. The performance of computer hardware is improved and the form of hardware is changed, but basically the change in mechanism was not occurred. Typically, the data used in the program is resident in memory during the operation because of the operating system efficiency. So, these data in memory is accessible through the memory dumps or real-time memory analysis. The user's personal information or confidential data may be leaked by exploiting data; thus, the countermeasures should be provided. In this paper, we proposed the method that minimizes user's data leakage through finding the physical memory address of the process using virtual memory address, and initializing memory data of the process.

• The Journal of the Korea Contents Association
• /
• v.15 no.9
• /
• pp.639-651
• /
• 2015

The purpose of this study is to examine the effects of knowledge base and metamemory in children's conceptual implicit memory with category-exemplar-generation task. Subjects were total 180 children of each 60 from Grade2, Grade6 and High school students. They were examined implicit memory with category-exemplar-generation task, knowledge base test, and metamemory test. The data were analyzed using ANCOVA, and Scheffe post hoc test. The result was following: First, as the child grow old, implicit memory primed increased. Implicit memory amount was significantly different between Grade2 and High school students, Grade6 and High school students. Second, as the child grow high knowledge base, implicit memory primed increased. There was a significantly different found between age and knowledge base. Third, as the child grow high metamemory, implicit memory primed increased. These results were interpreted as that the state of the age, knowledge base and metamemory should be an important factorin implicit memory. And current findings suggest that implicit memory can show development if a children's knowledge base and metamemory in developing with age.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.427-427
• /
• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• ETRI Journal
• /
• v.30 no.3
• /
• pp.483-485
• /
• 2008

A micro-sensor network is comprised of a large number of small sensors with limited memory capacity. Current key-establishment schemes for symmetric encryption require too much memory for micro-sensor networks on a large scale. In this paper, we propose a memory-efficient hypercube key establishment scheme that only requires logarithmic memory overhead.