• Speech Sciences
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• v.10 no.2
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• pp.65-75
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• 2003

This paper describes the issues associated with the real-time implementation of G.723.1A dual-rate speech coder on a TMS320VC5402 DSP. Firstly, the main features of the G.723.1A speech coder and the procedure involved in the implementation using assembly and C languages are discussed. Various real-time implementation issues such as memory/MIPS tradeoffs are also presented. For fixed-point implementation, we converted the ITU-T fixed-point ANSI C code into TMS320VC5402 code in the bit-exact way through verification using the test vectors. Finally, as the result of implementation, we present the MIPS and memory requirement for the real-time operation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.327-334
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• 1991

This paper proposes an efficient method of implementing the generalized Hough transform (GHT), which has been hindered by an excessive computing load and a large memory requirement. The conventional algorithm requires a parameter space of 4 dimensions in detection a rotated, scaled, and translated object in an input image. Prior to the application of GHT to the input image, the proposed method determines the angle of rotation and the scaling factor of the test image using the proportion of the edge components between the reference image and test image. With the rotation angle and the scaling factor already determined, the parameter spaceis to be reduced to a simple array of 2 dimensions by applying the unit GHT only one time. The experiments with the image of airplanes reveal that both of the computing time and the requires memory size are reduced by 95 percent, without any degradatationof accuracy, compared with the conventional GHT algorithm.

• Journal of the Korea Society of Computer and Information
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• v.1 no.1
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• pp.95-104
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• 1996

The Hough transform Is a robust technique Which Is useful in defecting straight lines in an picture. However, the extension of the conventional Hough transform to recover circles and ellipses has been limited by slow speed and excessive memory .This paper presents a method of detecting ellipses from the Image by using Least Square Method. This method Is reduced calculation cost and memory requirement .When detecting ellipse. Instead of obtaining accumulation of Hough transform for determination of ellipse parameters. particular points containing geometric properties of ellipse are selected. Parameters of the ellipse are calculated by Least Square Method using those particular points.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.159-165
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• 1994

In this paper, we propose a multi-layer associative neural network structure suitable for hardware implementaion with the function of performance refinement and improved robutst capability. Unlike other methods which reduce network complexity by putting restrictions on synaptic weithts, we are imposing a requirement of hidden layer neurons for the function. The proposed network has synaptic weights obtainted by Hebbian rule between adjacent layer's memory patterns such as Kosko's BAM. This network can be extended to arbitary multi-layer network trainable with Genetic algorithm for getting hidden layer memory patterns starting with initial random binary patterns. Learning is done to minimize newly defined network error. The newly defined error is composed of the errors at input, hidden, and output layers. After learning, we have bidirectional recall process for performance improvement of the network with one-shot recall. Experimental results carried out on pattern recognition problems demonstrate its performace according to the parameter which represets relative significance of the hidden layer error over the sum of input and output layer errors, show that the proposed model has much better performance than that of Kosko's bidirectional associative memory (BAM), and show the performance increment due to the bidirectionality in recall process.

• Journal of Korea Multimedia Society
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• v.6 no.5
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• pp.824-830
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• 2003

RPA (Recursive Partition Averaging) method was proposed in order to improve the storage requirement and classification rate of the Memory Based Reasoning. That algorithm worked well in many areas, however, the major drawbacks of RPA are it's pattern averaging mechanism. We propose an adaptive OHC algorithm which uses the FPD(Feature-based Population Densimeter) to increase the classification rate of RPA. The proposed algorithm required only approximately 40% of memory space that is needed in k-NN classifier, and showed a superior classification performance to the RPA. Also, by reducing the number of stored patterns, it showed a excellent results in terms of classification when we compare it to the k-NN.

• Design & Manufacturing
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• v.10 no.2
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• pp.50-54
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• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1849-1857
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• 1999

We proposed the RPA (Recursive Partition Averaging) method in order to improve the storage requirement and classification rate of the Memory Based Reasoning. This algorithm recursively partitions the pattern space until each hyperrectangle contains only those patterns of the same class, then it computes the average values of patterns in each hyperrectangle to extract a representative. Also we have used the mutual information between the features and classes as weights for features to improve the classification performance. The proposed algorithm used 30~90% of memory space that is needed in the k-NN (k-Nearest Neighbors) classifier, and showed a comparable classification performance to the k-NN. Also, by reducing the number of stored patterns, it showed an excellent result in terms of classification time when we compare it to the k-NN.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.339-349
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• 2011

IBDI (Internal Bit Depth Increase) is able to significantly improve the coding efficiency of high definition video compression by increasing the bit depth (or precision) of internal arithmetic operation. However the scheme also increases required internal memory for storing decoded reference frames and this can be significant for higher definition of video contents. So, the reference frame memory compression method is proposed to reduce such internal memory requirement. The reference memory compression is performed on 4x4 block called the processing unit to compress the decoded image using the correlation of nearby pixel values. This method has successively reduced the reference frame memory while preserving the coding efficiency of IBDI. However, additional information of each processing unit has to be stored also in internal memory, the amount of additional information could be a limitation of the effectiveness of memory compression scheme. To relax this limitation of previous memory compression scheme, we propose a selective merging-based reference frame memory compression algorithm, dramatically reducing the amount of additional information. Simulation results show that the proposed algorithm provides much smaller overhead than that of the previous algorithm while keeping the coding efficiency of IBDI.