• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1199-1203
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• 2010

Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.31-38
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• 2015

Nowadays, large size flash memory drives with more than a couple of hundreds of gigabytes are common. This paper presents an efficient cache management scheme of flash translation layer, called TPC-FTL, for large size flash memory drives. Since flash drives of large size usually contain large size RAM, we can enhance the performance of page mapping cache by using more RAM for the cache. But if the size exceeds a threshold, the existing schemes are impractical for real devices, because the time for cache manipulation becomes too long. TPC-FTL manages the cache in translation page unit, not in logical page number unit used in existing schemes. Since a translation page covers a large number of logical page numbers (for example, 512 for 2KB size page), the number of cache elements can be reduced up to a practical level. A performance evaluation shows that average response time, an important performance measure, is better than existing schemes via the effect of utilizing spacial locality in addition to temporal locality.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.55-67
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• 2005

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate Performance estimation. Since local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology arc validated by two real -life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

• ETRI Journal
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• v.35 no.1
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• pp.154-157
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• 2013

This letter proposes a memory-based parallel string matching engine using the compressed state transitions. In the finite-state machines of each string matcher, the pointers for representing the existence of state transitions are compressed. In addition, the bit fields for storing state transitions can be shared. Therefore, the total memory requirement can be minimized by reducing the memory size for storing state transitions.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.111-120
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• 2005

A cost effective three-dimensional color gamut mapping architecture is described. The conventional three-dimensional reduced resolution look-up table is considered and the concept of three-dimensional reduced resolution difference look-up table is introduced for cost effective and real-time color gamut mapping. The overall architecture uses one-dimensional memory decomposition of three-dimensional gamut mapping look-up table, three-dimensional interpolation and simple addition operation for generating the final gamut mapped colors. The required computational cost is greatly reduced by look-up table resolution adjustment and further reduced by the gamut mapping rule modification. The proposed architecture greatly reduces the required memory size and hardware complexity compared to the conventional method and it is suitable for real-time applications. The proposed hardware is suitable for FPGA and ASIC implementation and could be applied to the real-time display quality enhancement purposes.

• Journal of the Korea Computer Graphics Society
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• v.6 no.4
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• pp.35-42
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• 2000

3D texture mapping generates highly natural visual effects in which objects appear carved from lumps of materials rather than laminated with thin sheets as in 2D texture mapping. Storing 3D texture images in a table for fast mapping computations, instead of evaluating procedures on the fly, however, has been considered impractical due to the extremely high memory requirement. Recently, a practical real-time 3D texture mapping technique was proposed in [11], where they attempt to resolve the potential texture memory problem by compressing 3D textures using a wavelet-based encoding method. In this paper, we consider two other encoding schemes that could also be applied to the compression-based 3D texture mapping. In particular, we extend the vector quantization and FXT1 for 3D texture compression, and compare their performance with the wavelet-based encoding scheme.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.213-222
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• 2003

Most existing algorithms adopt the forward mapping method that is based on vector representation. Problem of existing algorithms Is the exponential increase of memory usage with number of layers. This degrades the accuracy of the boundary pattern representation. Our method uses bitmap representation and does not require any additional post-processing for conversion of vector-form results to bitmap-form. A new and efficient algorithm is presented in this paper for the generation of hyperbolic patterns by means of backward mapping methods.

• The Korean Journal of Nuclear Medicine
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• v.32 no.3
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• pp.225-237
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• 1998

Purpose: We investigated the statistical methods to compose the functional brain map of human working memory and the principal factors that have an effect on the methods for localization. Materials and Methods: Repeated PET scans with successive four tasks, which consist of one control and three different activation tasks, were performed on six right-handed normal volunteers for 2 minutes after bolus injections of 925 MBq $H_2^{15}O$ at the intervals of 30 minutes. Image data were analyzed using SPM96 (Statistical Parametric Mapping) implemented with Matlab (Mathworks Inc., U.S.A.). Images from the same subject were spatially registered and were normalized using linear and nonlinear transformation methods. Significant difference between control and each activation state was estimated at every voxel based on the general linear model. Differences of global counts were removed using analysis of covariance (ANCOVA) with global activity as covariate. Using the mean and variance for each condition which was adjusted using ANCOVA, t-statistics was performed on every voxel To interpret the results more easily, t-values were transformed to the standard Gaussian distribution (Z-score). Results: All the subjects carried out the activation and control tests successfully. Average rate of correct answers was 95%. The numbers of activated blobs were 4 for verbal memory I, 9 for verbal memory II, 9 for visual memory, and 6 for conjunctive activation of these three tasks. The verbal working memory activates predominantly left-sided structures, and the visual memory activates the right hemisphere. Conclusion: We conclude that rCBF PET imaging and statistical parametric mapping method were useful in the localization of the brain regions for verbal and visual working memory.