• 한국통신학회논문지
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• 제41권9호
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• pp.1108-1119
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• 2016

본 논문에서는 스마트폰의 저주파 대역 누설 전자파가 미치는 악영향을 분석하기 위해 스마트폰 모델별로 기본 동작에 따라 누설되는 30 MHz 이하의 누설 전자파 신호의 스펙트럼 특성 및 방사 패턴을 분석하였다. 사용자와의 직접적인 인터페이스를 담당하는 스마트폰의 입출력 센서 모듈(터치스크린, 카메라, 마이크 및 스피커 모듈)을 활성화시키는 4가지 기본 동작 모드에 의해 누설되는 전자파 신호를 상용 Near-Field 마그네틱 프로브를 통해 1cm의 격자 간격으로 정밀하게 측정하였다. 측정된 누설 전자파 신호를 분석한 결과, 스마트폰의 모델 및 동작 모드별로 누설되는 저주파 대역 전자파는 특이한 피크(Peak) 또는 하모닉(Harmonic) 피크 성분을 보이며, 동작 모드에 따라 각각의 입출력 센서 모듈이 활성화될 경우 해당 센서 모듈 및 메인보드 상의 AP(Application Processor), 메모리 주위로 상대적으로 강한 저주파 대역의 전자파가 누설되는 것을 확인할 수 있었다.

• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.47-52
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• 2002

A processing method is developed for preparing sol-gel derived $Pb(Zr_{1-x}Ti_x)O_3$ (x=0.5) thin films on Pt-Ir($Pt_{80}Ir_{20}$)-alloy substrates. The as-deposited layer was dried on a plate in air at $70^{\circ}C$. And then it was baked at $1500^{\circ}C$, annealed at $450^{\circ}C$ and finally annealed for crystallization at various temperatures ranging from $580^{\circ}C$ to $700^{\circ}C$ for 1hour in a tube furnace. The thickness of the annealed film with three layers was $0.3{\mu}m$. Crystalline properties and surface morphology were examined using X-ray diffractometer (XRD). Electrical properties of the films such as dielectric constant, C-V, leakage current density were measured under different annealing temperature. The PZT thin film which was crystallized at $600^{\circ}C$ for 60minutes showed the best structural and electrical dielectric constant is 577. C-V measurement show that $700^{\circ}C$ sample has window memory volt of 2.5V and good capacitance for bias volts. Leakage current density of every sample show $10^{-8}A/cm^2$ r below and breakdown voltage(Vb) is that 25volts.

• 한국재료학회지
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• 제34권6호
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• pp.283-290
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• 2024

The aggressive scaling of dynamic random-access memory capacitors has increased the need to maintain high capacitance despite the limited physical thickness of electrodes and dielectrics. This makes it essential to use high-k dielectric materials. TiO₂ has a large dielectric constant, ranging from 30~75 in the anatase phase to 90~170 in rutile phase. However, it has significant leakage current due to low energy barriers for electron conduction, which is a critical drawback. Suppressing the leakage current while scaling to achieve an equivalent oxide thickness (EOT) below 0.5 nm is necessary to control the influence of interlayers on capacitor performance. For this, Pt and Ru, with their high work function, can be used instead of a conventional TiN substrate to increase the Schottky barrier height. Additionally, forming rutile-TiO₂ on RuO₂ with excellent lattice compatibility by epitaxial growth can minimize leakage current. Furthermore, plasma-enhanced atomic layer deposition (PEALD) can be used to deposit a uniform thin film with high density and low defects at low temperatures, to reduce the impact of interfacial reactions on electrical properties at high temperatures. In this study, TiO₂ was deposited using PEALD, using substrates of Pt and Ru treated with rapid thermal annealing at 500 and 600 ℃, to compare structural, chemical, and electrical characteristics with reference to a TiN substrate. As a result, leakage current was suppressed to around 10^-6 A/cm² at 1 V, and an EOT at the 0.5 nm level was achieved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• ETRI Journal
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• 제35권4호
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• pp.734-737
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• 2013

Nonvolatile ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) memory based on an organic thin-film transistor with inkjet-printed dodecyl-substituted thienylenevinylene-thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of -12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 $cm^2/Vs$, $10^5$, and $10^{-10}$ A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.23-26
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• 2003

The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국전기전자재료학회논문지
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• 제25권2호
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• pp.100-104
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• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.436-441
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• 1998

$Pt/SrTiO_3/Pb_x(Zr_{0.52}, Ti_{0.48})O_3/SrTiO_3/Si$ structure was prepared by rf-magnetron sputtering method for use in nondestructive read out ferroelectric RAM(NDRO-FEAM). PBx(Zr_{0.52}Ti_{0.48})O_3}$(PZT) and $SrTiO_3$(STO) films were deposited respectively at the temperatures of $300^{\circ}C and 500^{\circ}C$on p-Si(100) substrate. The role of the STO film as a buffer layer between the PZT film and the Si substrate was studied using X-ray diffraction (XRD), Auger electron spectroscopy (ASE), and scanning electron microscope(SEM). Structural analysis on the interfaces was carried out using a cross sectional transmission electron microscope(TEM). For PZT/Si structure, mostly Pb deficient pyrochlore phase was formed due to the serious diffusion of Pb into the Si substrate. On the other hand, for STO/PZT/STO/Si structure, the PZT film had perovskite phase and larger grain size with a little Pb interdiffusion. the interfaces of the PZT and the STO film, of the STO film and the interface layer and $SiO_2$, and of the $SiO_2$ and the Si substate had a good flatness. Across sectional TEM image showed the existence of an amorphous layer and $SiO_2$ with 7nm thickness between the STO film and the Si substrate. The electrical properties of MIFIS structure was characterized by C-V and I-V measurements. By 1MHz C-V characteristics Pt/STO(25nm)/PZT(160nm)/STO(25nm)/Si structure, memory window was about 1.2 V for and applied voltage of 5 V. Memory window increased by increasing the applied voltage and maximum voltage of memory window was 2 V for V applied. Memory window decreased by decreasing PZT film thickness to 110nm. Typical leakage current was abour $10{-8}$ A/cm for an applied voltage of 5 V.