• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.79-89
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• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.71-79
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• 2012

As advances in computer technology, dissemination of smartphones and tablet PCs has increased and digital media has become easily accessible. The performance of computer hardware is improved and the form of hardware is changed, but basically the change in mechanism was not occurred. Typically, the data used in the program is resident in memory during the operation because of the operating system efficiency. So, these data in memory is accessible through the memory dumps or real-time memory analysis. The user's personal information or confidential data may be leaked by exploiting data; thus, the countermeasures should be provided. In this paper, we proposed the method that minimizes user's data leakage through finding the physical memory address of the process using virtual memory address, and initializing memory data of the process.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.652-655
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• 2003

The human being receives a new information from outside and the information shows gradual oblivion with time. But it remains in memory and isn't forgotten for a long time if the information is read several times over. For example, we assume that we memorize a telephone number when we listen and never remind we may forget it soon, but we commit to memory long time by repeating. If the human being received new information with strong stimulus, it could remain in memory without recalling repeatedly. The moments of almost losing one's life in on accident or getting a stroke of luck are rarely forgiven. The human being can keep memory for a long time in spite of the limit of memory for the mechanism mentioned above. In this paper, we will make a model explaining that mechanism using a neural network Adaptive Resonance Theory.

• International Journal of Contents
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• v.6 no.4
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• pp.22-29
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• 2010

In flash memory, many previous garbage collection methods only merge blocks statically and do not consider the contents of buffer. These schemes may cause more unnecessary block erase operations and page copy operations. However, since flash memory has the limitation of maximum rate and life cycle to delete each block, an efficient garbage collection method to evenly wear out the flash memory region is needed. This paper proposes a memory compaction scheme based on block-level buffer for flash memory. The proposed scheme not only merges the data blocks and the corresponding log block, but also searches for the block-level buffer to find the corresponding buffer blocks. Consequently, unnecessary potential page copying operations and block erasure operations could be reduced, thereby improving the performance of flash memory and prolonging the lifetime of flash memory.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.11
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• pp.461-470
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• 2013

This paper proposes high speed kernel data collection method for analysis of memory workload, using technique of direct access to process's memory management structure. The conventional analysis tools have a slower data collection speed and they are lack of scalability due to collection only formalized memory information. The proposed method collects kernel data much faster than the conventional methods using technique of direct collect to process's memory information, page table, page structure in the memory management structure, and it can collect data which user wanted. We collect memory management data of the running process, and analyze its memory workload.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.89-100
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• 2011

Physical memory analysis has been an issue on a field of live forensic analysis in digital forensics until now. It is very useful to make the result of analysis more reliable, because record of user behavior and data can be founded on physical memory although process is hided. But most memory analysis focuses on windows based system. Because the diversity of target system to be analyzed rises up, it is very important to analyze physical memory based on other OS, not Windows. Mac OS X, has second market share in Operating System, is operated by loading kernel image to physical memory area. In this paper, We propose a methodology for physical memory analysis on Mac OS X using symbol information in kernel image, and acquire a process information, mounted device information, kernel information, kernel extensions(eg. KEXT) and system call entry for detecting system call hooking. In additional to the methodology, we prove that physical memory analysis is very useful though experimental study.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.4
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• pp.919-928
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• 2018

Out-Of-Bounds (OOB) is one of the most powerful vulnerabilities in heap memory. The OOB vulnerability allows an attacker to exploit unauthorized access to confidential information by tricking the length of the array and reading or writing memory of that length. In this paper, we propose a method to automatically detect OOB vulnerabilities in heap memory using dynamic symbol execution and shadow memory table. First, a shadow memory table is constructed by hooking heap memory allocation and release function. Then, when a memory access occurs, it is judged whether OOB can occur by referencing the shadow memory, and a test case for causing a crash is automatically generated if there is a possibility of occurrence. Using the proposed method, if a weak block search is successful, it is possible to generate a test case that induces an OOB. In addition, unlike traditional dynamic symbol execution, exploitation of vulnerabilities is possible without setting clear target points.

• Korean Journal of Biological Psychiatry
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• v.23 no.3
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• pp.102-107
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• 2016

This review will summarize EEG studies of learning and memory based on frequency bands including theta waves (4-7 Hz), gamma waves (> 30 Hz) and alpha waves (7-12 Hz). Authors searched and reviewed EEG papers especially focusing on learning and memory from PubMed. Theta waves are associated with acquisition of new information from stimuli. Gamma waves are connected with comparing and binding old information in preexisting memory and new information from stimuli. Alpha waves are linked with attention. Eventually it mediates the learning and memory process. Although EEG studies of learning and memory still have controversial issues, the future EEG studies will facilitate clinical benefits by virtue of more developed and encouraging prospects.