• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.90-100
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• 1997

In this paper, we propose a new optical thresold generator as a key-stream genrator for stream cipher systems. The random key-bit stream is generated by a digital generator that is composed of LFSRs and nonlinear ligics. Digital implementatin of a key-stream generator requires large memory to implement programmable tapping points. This memory problem may be overcome easily by using the proposed optical system which has the proberty of 2D parallel processing.To implement hte threshold generator optically, we use conventional twisted nematic type SLMs (LCDs). This proposed system is based on the shadow casting technique for the AND operation between taps and sregister stages. It is also based on the proposed PMRS method for modulo 2 addition. The proposed PMRS method uses the property of light's polarization on LCD and can be implemented optically using one LCD and some mirrors. One of the major advantages of the proosed system is that there is no limitation of the number of the progarmmable tapping points. Therefore, the proposed system can be applied for the 2D encryption system which processes large amounts of data such as 2D images. We verify the proposed system with some simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.34-38
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• 1984

The master key on the multiuser MH public key cryptosystem, can be substituted for multiple private keys, is proposed and derived. Applying it to public key cryptosystem, it can be possible to save memory size by selecting the master key and easy to authenticate the truth of message and the identity of the sender. Vsing this master key, it is proved that the encryption time ratio of MH method is smaller than that of RSA's method.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.54 no.4
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• pp.217-223
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• 2005

In this paper, we have proposed a secure dynamic ID allocation protocol using mutual authentication on the RFID tag. Currently, there are many security protocols focused on the low-price RFID tag. The conventional low-price tags have limitation of computing power and rewritability of memory. The proposed secure dynamic ID allocation protocol targets to the high-performance RFID tags which have more powerful performance than conventional low-price tag by allocating a dynamic ID to RFID using mutual authentication based on symmetric encryption algorithm. This protocol can be used as a partial solution for ID tracing and forgery.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.1128-1130
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• 1999

Optical encoding method of images using random-phase encoding in both input and Fourier Planes was proposed by Javidi and his group, and the method was realized experimentally by Singh and his group with use of a photorefractive crystal and a phase conjugate wave.[1-2] Recently various techniques have been proposed theorically and experimentally. These include the method using one random-phase mask in the Fourier plane or two random-phase masks in the input and the Fresnel planes.[3] We demonstrate the difference and the problem of the methods using one or two random-phase masks in the Fourier or Fresnel plane. We perform the encoding and decoding in $LiNbO_3$ crystal using degenerate four-wave mixing.

• Current Industrial and Technological Trends in Aerospace
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• v.9 no.1
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• pp.90-101
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• 2011

In this article, we introduce the technologies and trend of technical evolution of Payload Data Handling Unit (PDHU) for Earth Observation Satellites. As well, we review the efforts for the Koreanization of PDHU so far, and conclude with some suggestions for future work.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.914-916
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• 2011

최근 낸드 플래시 메모리 기술의 발전으로 플래시 메모리의 용량이 증가함에 따라 다양한 장치에서 데이터 저장소로 사용되고 있으며, 하드디스크를 대체할 저장 매체로서 주목을 받고 있다. 하지만 낸드 플래시 메모리의 특성으로 인해 데이터를 삭제하더라도 일정 기간 삭제된 데이터가 메모리에 남아있게 되며, 이러한 특성으로 사용자의 중요 데이터가 보호되지 않은 상태로 저장되어 외부에 노출될 수 있다. 따라서 이런 특성을 보완하는 방법이 필요하며 본 논문에서는 낸드 플래시 메모리의 단점을 해결하기 위하여 낸드 플래시 메모리를 위한 시스템 소프트웨어인 FTL(Flash Translation Layer) 계층에서 암호화 알고리즘을 사용하여 데이터를 노출하지 않게 하는 방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• Convergence Security Journal
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• v.21 no.2
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• pp.29-35
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• 2021

UART (Universal asynchronous receiver/transmitter) is a hardware device that converts data into serial format and transmits it, and is widely used for system diagnosis and debugging in most embedded systems. Hackers can access system memory or firmware by using the functions of UART, and can take over the system by acquiring administrator rights of the system. In this paper, we studied secure UART to protect against hacker attacks through UART. In the proposed scheme, only authorized users using the promised UART communication protocol are allowed to access UART and unauthorized access is not allowed. In addition, data is encrypted and transmitted to prevent protocol analysis through sniffing. The proposed UART technique was implemented in an embedded Linux system and performance evaluation was performed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.1-6
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• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.