• Korean Journal of Digital Imaging in Medicine
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• v.12 no.2
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• pp.81-87
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• 2010

The setting parameters of ultrasound scanner give influences to change of image. Sonographers have used a Matlab program to make Low Contrast Sensitivity(LCS) value and compared original images in order to evaluate the use of the supersonic diagnosis machinery. We confirmed the change of image in Grayscale values using Photoshop program. Experiment equipment of our research used A Medison Accuvix V10, A Multi-Tissue Ultrasound Phantom(040 GSE) of CHRIS Company, A Adobe Photoshop CS4 Program, A Convex Probe, A USB memory stick, A Probe Fixation Equipment. The method used Gain, Dynamic Range(DR) of the setting parameters of ultrasound scanner and researched Gain and DR was set to 10 dB. We changed the different settings to see the changes of images using Grayscale values of a Photoshop program about tissue images of a phantom. This study evaluated DR and Gain whether it is an image controller to get the optimum contrast to produce an image to see the how effect on the images. We did not use Gateway in supersonic diagnosis machinery. We can easily open to open the files through Photoshop program before we get Digital Imaging and Communications in Medicine(DICOM) files use USB memory stick in supersonic diagnosis machinery. When we diagnosed the lesion of the patient with ultrasound, the contrast and the Gray scale value of image are very important. In this research, we determined the optimum setting parameters that provided useful information to diagnose disease and evaluated the change of improved images.

• Smart Structures and Systems
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• v.21 no.3
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• pp.257-262
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• 2018

Vibrational problems in the domestic Small Horizontal Axis Wind Turbines (SHAWT) are due to flap wise vibrations caused by varying wind velocities acting perpendicular to its blade surface. It has been reported that monitoring the structural health of the turbine blades requires special attention as they are key elements of a wind power generation, and account for 15-20% of the total turbine cost. If this vibration problem is taken care, the SHAWT can be made as commercial success. In this work, Shape Memory Alloy (SMA) wires made of Nitinol (Ni-Ti) alloys are embedded into the Glass Fibre Reinforced Polymer (GFRP) wind turbine blade in order to reduce the flapwise vibrations. Experimental study of Nitinol (Ni-Ti) wire characteristics has been done and relationship between different parameters like current, displacement, time and temperature has been established. When the wind turbine blades are subjected to varying wind velocity, flapwise vibration occurs which has to be controlled continuously, otherwise the blade will be damaged due to the resonance. Therefore, in order to control these flapwise vibrations actively, a non-linear current controller unit was developed and fabricated, which provides actuation force required for active vibration control in smart blade. Experimental analysis was performed on conventional GFRP and smart blade, depicted a 20% increase in natural frequency and 20% reduction in amplitude of vibration. With addition of active vibration control unit, the smart blade showed 61% reduction in amplitude of vibration.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.635-642
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• 2004

The traditional communication protocols such as TCP/IP are not suitable for PC cluster systems because of their high software processing overhead. To eliminate this overhead, industry leaders have defined the Virtual Interface Architecture (VIA). VIA provides two different data transfer mechanisms, a traditional Send/Receive model and the Remote Direct Memory Access (RDMA) model. RDMA is extremely efficient way to reduce software overhead because it can bypass the OS and use the network interface controller (NIC) directly for communication, also bypass the CPU on the remote host. In this paper, we have implemented VIA-based RDMA mechanism in hardware. Compared to the traditional Send/Receive model, the RDMA mechanism improves latency and bandwidth. Our RDMA mechanism can also communicate without using remote CPU cycles. Our experimental results show a minimum latency of 12.5${\mu}\textrm{s}$ and a maximum bandwidth of 95.5MB/s. As a result, our RDMA mechanism allows PC cluster systems to have a high performance communication method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.769-776
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• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.27-33
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• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.342-347
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• 2002

After the industrial revolution in 20 century, the world are preparing for new revolution that is society with knowledge for a basis such as IT(Information Technology), NT(Nano Technology) and BT(Bio Technology). Recently, NT is applied to various fields that are composed of science, industry, media and semiconductor-micro technology. It has need of IT that is ultra-precision positioning technology with strokes of many hundreds mm and maintenance of nm precision in fields of ultra micro process, ultra precision measurement, photo communication part and photo magnetic memory. Performance test of servo control system that is used ultra-precision positioning system with single plane X-Y stage is performed by simulation with Matlab. Analyzed for previous control algorithm and adapted for modern control theory, dual servo algorithm is developed by minimum order observer, and stability and priority on controller are secured. Through the simulation and experiments on ultra precision positioning, stability and priority on ultra-precision positioning system with single plane X-Y stage and control algorithm are secured by using Matlab with Simulink and ControlDesk made in dSPACE

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.444-448
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• 2005

This paper presents a developing procedure of the CAN-based real-time simulator for car body control, aiming at replacing the actual W/H (Wiring Harness) and J/B(Junction Box) couple eventually. The CAN protocol, as one kind of field-bus communication, defines the lowest 2 layers of the ISO/OSI standard, namely, the physical layer(PL) and the data link layer(DLL), for which the CSMA/NBA protocol is generally adopted. For CPU, two PIC18Fxx8x's are used because of their built-in integration of CAN controller, large internal FLASH memory (48K or 64K), and their costs. To control J/B's and actuators, 2 controller boards are separately implemented, between which CAN lines communicate through CAN transceivers MCP255. A power motor for washing windshield, 1 door lock motor, and 6 blink lamps are chosen for actuators of the simulator for the first stage. For the software architecture, a polling method is used for the fast global response time despite its slow individual response time. To improve the individual response time and to escape from some eventual trapped-function loops, High/Low ports of the CPU are simply used, which increases the stability of the actuator modules. The experimental test shows generally satisfactory results in normal transmitting / receiving function and message trace function. This simulator based on CAN shows a promising usefulness of lighter, more reliable and intelligent distributed body control approach than the conventional W/H and J/B couple. Another advantage of this approach lies in the distributed control itself, which gives better performance in hard real-time computing than centralized one, and in the ability of integrating different modules through CAN.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.