• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.583-591
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• 2000

Caching mechanisms have been studied extensively to buffer the speed gap of hierarchical storages in the context of cache memory, paging system, and buffer management system. As the wide-area distributed environments such as the WWW extend broadly, caching of remote objects becomes more and more important. In the wide-area distributed environments, the cost and the benefit of caching an object is not uniform due to the location of the object; which should be considered in the cache replacement algorithms. For online operation, the time complexity of the replacement algorithm should not be excessive. To date, most replacement algorithms for the wide-area distributed environments do not meet both the non-uniformity of objects and the time complexity constraint. This paper proposes a replacement algorithm which considers the non-uniformity of objects properly; it also allows for an efficient implementation. Trace-driven simulations show that proposed algorithm outperforms existing replacement algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.420-430
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• 2000

Several caching schemes for realtime multimedia systems have been proposed, but they focus only on increasing the hit ratio without providing any means to utilize the saved disk bandwidth due to cache hits. One of the most important metrics in multimedia systems is the number of clients that the systems can service simultaneously guaranteeing Quality of Service(QoS). Preemptive but Safe Interval Caching(PSIC) was proposed as a caching scheme which makes it possible to provide deterministic QoS.. However, it has no ability to adapt to the change of system environments since it has no mechanism to change the cache size. In this paper, we present a new caching scheme, Dynamic Interval Caching(DIC), which maximizes the performance, regardless of the change of system environments, providing hiccup-free service, by managing memory buffers dynamically. And it is demonstrated that DIC allocates buffer cache optimally, by comparing with PSIC through trace-driven simulations.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.395-404
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• 1999

포인터 스위즐링 기법은 포인터 스위즐링과 언스위즐링으로 이루어지며, 포인터 스위즐링은 객체 접근 시 객체 식별자를 해당 객체의 메모리 주소로 교체하는 것을 말하며, 언스위즐링은 객체 교체 또는 객체 저장 시에 스위즐링된 포인터를 원래의 객체 식별자로 환원하는 것을 말한다. 본 연구에서는 시스템 버퍼 구조에 따라 여러 포인터 스위즐링 기법을 분류하여 장단점을 분석하였으며, 이중 버퍼 구조 상에서 적극/소극, 직접/간접 스위즐링, 언스위즐링 모듈을 설계, 구현하였다. 또한 제한된 크기의 객체 버퍼 상에서 각 포인터 스위즐링 모듈의 성능을 평가하였다. 이 성능 평가의 결과로는 사용하지 않는 포인터는 스위즐링하지 않으며 언스위즐링 부담이 적은 소극 간접 스위즐링 기법이 일반적으로 뛰어난 성능을 나타냄을 알 수 있게 되었다.Abstract The pointer swizzling methods consist of pointer swizzling and unswizzling. Pointer swizzling replaces the OID of a object to the memory address of the object at object access time and unswizzling replaces the swizzling pointer of the OID at object replacement time or object save time. In this research, the different techniques for pointer swizzling are classified according to the system buffer structure and analyzed the pros and cons. In addition, eager/lazy, direct/indirect swizzling, unswizzling modules are designed and implemented on a dual buffering structure. Also, we evaluate the performance of pointer swizzling modules on the restricted object buffer size. The results of performance evaluation show that the performance of lazy indirect pointer swizzling technique is generally good because unused pointers are not swizzled, and unswizzling overhead is minimized.

• Journal of KIISE
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• v.42 no.2
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• pp.169-176
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• 2015

The atomic write technique is a good solution to solve the problem of the double write buffer. The atomic write technique needs modified I/O subsystems (i.e., file system and I/O schedulers) and a special SSD that guarantees the atomicity of the write request. In this paper, we propose the writing unit aligned block allocation technique (for EXT4 file system) and the merge prevention of requests technique for the CFQ scheduler. We also propose an atomic write-supporting SSD which stores the atomicity information in the spare area of the flash memory page. We evaluate the performance of the proposed atomic write scheme in MariaDB using the tpcc-mysql and SysBench benchmarks. The experimental results show that the proposed atomic write technique shows a performance improvement of 1.4~1.5 times compared to the double write buffer technique.

• Journal of KIISE
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• v.42 no.8
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• pp.1049-1056
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• 2015

Runtime Intrusion Prevention Evaluator (RIPE), published in 2011, is a benchmark suite for evaluating mitigation techniques against 850 attack patterns using only buffer overflow. Since RIPE is built as a single process, defense and attack routines cannot help sharing process states and address space layouts when RIPE is tested. As a result, attack routines can access the memory space for defense routines without restriction. We separate RIPE into two independent processes of defense and attacks so that mitigations based on confidentiality such as address space layout randomization are properly evaluated. In addition, we add an execution mode to test robustness against brute force attacks. Finally, we extend RIPE by adding 38 attack forms to perform format string attacks and virtual table (vtable) hijacking attacks. The revised RIPE contributes to the diversification of attack patterns and precise evaluation of the effectiveness of mitigations.

• Journal of Korea Society of Industrial Information Systems
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• v.15 no.2
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• pp.31-39
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• 2010

VoD(Video-on-Demand) servers have to provide timely processing guarantees for continuous media and reduce the storage and bandwidth requirements for continuous media. The compression techniques make the bit rates of compressed video data significantly variable from frame to frame. A VoD system should be able to provide the client with interactive operations such as fast forward and fast rewind in addition to normal playback of movie. However, interactive operations require additional resources such as storage space, disk bandwidth, memory and network bandwidth. In a stored video application such as VoD system, it is possible that a priori disk access patterns can be used to reserve the system resources in advance. In addition, clients of VoD server spend most of their time in playback mode and the period of time spent in interactive mode is relatively small. In this paper, I present the new buffer management scheme that provides efficient support for interactive operations in a VoD server using variable bit rate continuous media. Simulation results show that our strategy achieves 34% increase of the number of accepted clients over the LRU strategy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.662-672
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• 2011

This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.