• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.334-337
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• 2005

This paper describes the implementation of DCS communication network that provides high bandwidth and reliability. The network for DCS in this paper adopts the Reflective Memory (RM) architecture and Fast Ethernet physical media that have 100Mbps bandwidth. Also, this network uses Ring Enhancement Device (RED) which was invented to reduce the time delay of each node. The DCS network that is introduced in this paper is named as ERCNet(Ethernet based Real-time Control Network). This paper describes the architecture and working algorithms of ERCNet and performs numerical analysis. In addition, the performance of ERCNet is evaluated by experiment using the developed ERCNet network.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.403-404
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• 2008

In this paper, a new 4-way search window is developed for H.264 Motion Estimation(ME) to improve the memory bandwidth. The proposed 4-way(up, down, left, right) search window could improve the reuse of overlapped window data to reduce the redundancy access factor by 1.4, though the 1/3-way search window requires $7.7{\sim}11$ times of data retrieval redundantly. In experiments, the new implementation of 4-way search window on Altera Stratix-III could deal with CIF ($352{\times}288$) video of 3 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps real time at 55.2MHz.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.

• Journal of Energy Engineering
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• v.14 no.2 s.42
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• pp.112-116
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• 2005

This paper describes the implementation of DCS communication network that provides high bandwidth and reliability. The network for DCS in this paper adopts the Reflective Memory (RM) architecture and Fast Ethernet physical media that have 100 Mbps bandwidth. Also, This network uses Ring Enhancement Device (RED) which is invented to reduce the time delay of each node. The DCS network that is introduced in this paper is named as ERCNet (Ethernet based Real-time Control Network). This paper describes the architecture and working algorithms of ERCNet and performs numerical analysis. In addition, the performance of ERCNet is evaluated by experiment using the developed ERCNet network.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.8-13
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• 2023

High bandwidth memory a core technology of the future memory semiconductor industry, is attracting attention. Temporary bonding and debonding process technology, which plays an important role in high bandwidth memory process technology, is also being studied. In this process, total thickness variation is a major factor determining wafer performance. In this study, the reliability of the equipment measuring total thickness variation is identified, and the servo motor settling, and wafer total thickness variation measurement accuracy are analyzed. As for the experimental variables, vacuum, acceleration time, and speed are changed to find the most efficient value by comparing the stabilization time. The smaller the vacuum and the larger the radius, the longer the settling time. If the radius is small, high-speed rotation performance is good, and if the radius is large, low-speed rotation performance is good. In the future, we plan to conduct an experiment to measure the entire of the wafer.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.80-88
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• 1999

In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Geophysics and Geophysical Exploration
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• v.21 no.4
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• pp.213-219
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• 2018

In this study, we simulated 3D wave propagation modeling using a Xeon Phi x200 processor and compared the parallel computation performance with that using a Xeon CPU. Unlike the 1st generation Xeon Phi coprocessor codenamed Knights Corner, the 2nd generation x200 Xeon Phi processor requires no additional communication between the internal memory and the main memory since it can run an operating system directly. The Xeon Phi x200 processor can run large-scale computation independently, with the large main memory and the high-bandwidth memory. For comparison of parallel computation, we performed the modeling using the MPI (Message Passing Interface) and OpenMP (Open Multi-Processing) libraries. Numerical examples using the SEG/EAGE salt model demonstrated that we can achieve 2.69 to 3.24 times faster modeling performance using the Xeon Phi with a large number of computational cores and high-bandwidth memory compared to that using the 12-core CPU.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.