• Journal of IKEEE
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• v.20 no.3
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• pp.241-250
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• 2016

AVM(Around View Monitoring) is a function of ADAS(Advanced Driver Assistance Systems), which provides a bird's eye view of the surroundings of a vehicle to the user. AVM systems require large bandwidth since they are composed of four input images and require real-time processing for vehicle-embedded environments. Also, the memory bandwidth requirement increases greatly when the resolution of the input data is higher. In this paper, we propose four basic hardware models of AVM systems. The models are decided by whether or not there is a valid data extraction module and an image processing purpose LUT generation module. We analyze the required bandwidth and hardware resource for each model. For verification of the proposed models, we implemented an AVM system using XC7Z045 FPGA and DDR3 memory for VGA and FHD resolution. All four of the proposed hardware model is executed below 33ms, which shows that it can operate in real-time.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.205-212
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• 2003

In this paper, we propose a simple and efficient hardware-supported antialiasing algorithm and its rendering scheme. The proposed method can efficiently reduce the required memory bandwidth as well as memory size compared to a conventional supersampling when rendering 3D models. In addition, it can provide almost the same high quality scenes as supersampling does. In this paper, we have introduced the RUF (Recently Used Fragment) buffer that stores some or whole parts of a fragment or two more the merged results of fragments that recently used in color calculation. We have also proposed a color calculation algorithm to deteriorate the image quality as referencing the RUF buffer. Because of the efficiency presented in the proposed algorithm, the more number of sampling points increases the more memory saving ratio we can gain relative to the conventional supersampling. In our simulation, the proposed method can reduce the amount of memory size by 31% and the memory bandwidth by 11% with a moderate pixel color difference of 1.3% compared to supersampling for 8 sparse sampling points.

• Communications for Statistical Applications and Methods
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• v.26 no.6
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• pp.611-622
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• 2019

This paper considers the estimation of the long memory parameter in nonparametric regression with strongly correlated errors. The key idea is to minimize a unified mean squared error of long memory parameter to select both kernel bandwidth and the number of frequencies used in exact local Whittle estimation. A unified mean squared error framework is more natural because it provides both goodness of fit and measure of strong dependence. The block bootstrap is applied to evaluate the mean squared error. Finite sample performance using Monte Carlo simulations shows the closest performance to the oracle. The proposed method outperforms existing methods especially when dependency and sample size increase. The proposed method is also illustreated to the volatility of exchange rate between Korean Won for US dollar.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• Journal of electromagnetic engineering and science
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• v.9 no.3
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• pp.152-158
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• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• ETRI Journal
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• v.46 no.2
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• pp.205-217
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• 2024

We propose a bandwidth prediction approach based on deep learning. The approach is intended to accurately predict the bandwidth of various types of mobile networks. We first use a machine learning technique, namely, the gradient boosting algorithm, to recognize the connected mobile network. Second, we apply a handover detection algorithm based on network recognition to account for vertical handover that causes the bandwidth variance. Third, as the communication performance offered by 3G, 4G, and 5G networks varies, we suggest a bidirectional long short-term memory model with time distribution for bandwidth prediction per network. To increase the prediction accuracy, pretraining and fine-tuning are applied for each type of network. We use a dataset collected at University College Cork for network recognition, handover detection, and bandwidth prediction. The performance evaluation indicates that the handover detection algorithm achieves 88.5% accuracy, and the bandwidth prediction model achieves a high accuracy, with a root-mean-square error of only 2.12%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.68-74
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2725-2730
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• 2012

In this paper, for improving the H.264/AVC hardware performance, we propose an inter predictor hardware design using a multi reference frame selector and an implicit weighted predictor. previous reference frame are reused for Low Memory Bandwidth. The size of the reference memory in the predictor was reduced by about 46% and the external memory access rate was reduced by about 24% compared with the one in the reference software JM16.0. We designed the proposed system with Verilog-HDL and synthesized inter predictor circuit using the Magnachip 0.18um CMOS standard cell library. The synthesis result shows that the gate count is about 2,061k and the design can run at 91MHz.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.