• Title/Summary/Keyword: Memories

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Documenting Contemporary 'Counter-memories': Focused on the Yongsan Tragedy (동시대 '대항기억'의 기록화 용산참사 사례를 중심으로)

  • Lee, Kyong Rae;Lee, Kwang-Suk
    • The Korean Journal of Archival Studies
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    • no.53
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    • pp.45-77
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    • 2017
  • This study intends to rehabilitate the memories of the social other which have been gradually forgotten in the social events overloaded with the undemocratic violence in South Korea today. This study explores a case of Yongsan Tragedy in 2009 among the most tragic events. It notes the autonomous ways in which activist artists would like to memorize the socio-historical events anew despite the emptiness of public records. In other words, this study considers the Yongsan case to be significant that a group of the public, artists, grassroots activists, religion men got together in solidarity so as to create the contested narratives countering dominant memories and thus to signify the records written by the civil society. Among others, activist artists had documented the unofficial counter-memories of socially alienated peoples in terms of planning a series of artistic events such as opening some gallery exhibitions and performance events, issuing a volume of work books, comics and photographies, online broadcasting, and directing some documentaries. Especially, this paper tends to note the documentation of on-site activist artists to record the counter-memories against social oblivion. By doing so, it finally suggests how we could document the Yongsan Tragedy both to search out the archival implications of today's art activism and to insert those artistic records into the commonly shared counter-memories in a more inclusive way.

High-efficiency BIRA for embedded memories with a high repair rate and low area overhead

  • Lee, Joo-Hwan;Park, Ki-Hyun;Kang, Sung-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.266-269
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    • 2012
  • High-efficiency built-in redundancy analysis (BIRA) is presented. The proposed BIRA uses three techniques to achieve a high repair rate using spare mapping registers with adjustable fault tags to reduce area overhead. Simulation results show that the proposed BIRA is a reasonable solution for embedded memories.

Design of GBSB Neural Networks Using LMI (LMI를 이용한 GBSB 신경망 설계)

  • Cho, Hyuk;Park, Joo-Young;Park, Dai-Hee
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1997.10a
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    • pp.409-412
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    • 1997
  • In this paper, we propose a novel synthesis method of GBSB(Generalized BSB)-based neural autoassociative memories in which we analyze qualitative properties of GBSB model, recast a design problem of an associative memory to LMIP(Linear Matrix Inequality Problem), and optimize the LMIP using LMI techniques. The obtained memory satisfies many of the required properties of associative memories and has some peculiar properties. Comparing experimental results with those of others, we show its correctness and effectiveness.

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Built-in self test for testing neighborhood pattern sensitive faults in content addressable memories (Content addressable memory의 이웃패턴감응고장 테스트를 위한 내장된 자체 테스트 기법)

  • 강용석;이종철;강성호
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.8
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    • pp.1-9
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    • 1998
  • A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

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Implementation of Bidirectional Associative Memories Using the GBAM Model with Bias Terms (바이어스항이 있는 GBAM 모델을 이용한 양방향 연상메모리 구현)

  • 임채환;박주영
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2001.05a
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    • pp.69-72
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    • 2001
  • In this paper, we propose a new design method for bidirectional associative memories model with high error correction ratio. We extend the conventional GBAM model using bias terms and formulate a design procedure in the form of a constrained optimization problem. The constrained optimization problem is then transformed into a GEVP(generalized eigenvalue problem), which can be efficiently solved by recently developed interior point methods. The effectiveness of the proposed approach is illustrated by a example.

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Generalized Asymmetrical Bidirectional Associative Memory for Human Skill Transfer

  • T.D. Eom;Lee, J. J.
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.482-482
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    • 2000
  • The essential requirements of neural network for human skill transfer are fast convergence, high storage capacity, and strong noise immunity. Bidirectional associative memory(BAM) suffering from low storage capacity and abundance of spurious memories is rarely used for skill transfer application though it has fast and wide association characteristics for visual data. This paper suggests generalization of classical BAM structure and new learning algorithm which uses supervised learning to guarantee perfect recall starting with correlation matrix. The generalization is validated to accelerate convergence speed, to increase storage capacity, to lessen spurious memories, to enhance noise immunity, and to enable multiple association using simulation work.

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Characterization Method of Memory Compiler Using Reference Memories (기준 메모리를 이용한 메모리 컴파일러 특성화 방법)

  • Shin, Woocheol;Song, Hyekyoung;Jung, Wonyoung;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.38-45
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    • 2014
  • This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.