• Parasites, Hosts and Diseases
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• 제54권6호
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• pp.743-750
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• 2016

Mus musculus (Rodentia: Muridae) has generally been infected with a rodent hookworm Nippostrongylus brasiliensis. In this report, we present morphological and molecular identification of N. brasiliensis by light and scanning electron microscopy and PCR amplification of mitochondrial cytochrome c oxidase subunit 1 (cox1) gene and the protein sequences encoded by cox1 gene, respectively. Despite the use of N. brasiliensis in many biochemistry studies from India, their taxonomic identification was not fully understood, especially at the species level, and no molecular data is available in GenBank from India. Sequence analysis of cox1 gene in this study revealed that the present specimen showed close identity with the same species available in GenBank, confirming that the species is N. brasiliensis. This study represents the first record of molecular identification of N. brasiliensis from India and the protein structure to better understand the comparative phylogenetic characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.