• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.352-357
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• 2007

Since a pattern defects "repair" system using a diode pumped solid state laser for Flat Panel Display (FPD) was suggested, a lot of laser systems have been explored and developed for mass-production microfabrication process. A maskless lithography system using 405 nm violet laser and Digital Micromirror Device (DMD) has been developed for PDP and Liquid Crystal Display (LCD) Thin Film Transistor (TFT) photolithography process. In addition, a "Laser Direct Patterning" system for Indium Tin Oxide (ITO) for Plasma Display Panel(PDP) has been evaluated one of the best successful examples for laser application system which is applied for mass-production lines. The "heat" and "solvent" free laser microfabrications process will be widely used because the next-generation flat panel displays, Flexible Display and Organic Light Emitting Diode (OLED) should use plastic substrates and organic materials which are very difficult to process using traditional fabrication methods.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.5
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• pp.24-31
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• 2004

Masking effect of the nanoscratched silicon (100) surface was studied and applied to a maskless nanofabrication technique. First, the surface of the silicon (100) was machined by ductile-regime nanomachining process using the scratch option of the Nanoindenter${ \circledR}$ XP. To clarify the possibility of the nanoscratched silicon surfaces for the application to wet etching mask, the etching characteristic with a KOH solution was evaluated at room temperature. After the etching process, the convex nanostructures were made due to the masking effect of the mechanically affected layer. Moreover, the height and the width of convex structures were controlled with varying normal loads during nanoscratch.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.829-834
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• 2011

Exposure process is the most important technology to fabricate highly integrated circuit. Up to now, mask type lithography process has been generally used. However, it is not efficient for small quantity and/or frequently changing products. Therefore, maskless lithography technology is raised in exposure process. In this study, relations between multi-beam energy and overlay were analyzed. Exposure experiment of generating pattern was performed. It was from presented scan line by multi- beam simulation. As a result, optimal scan line distance was proposed by simulation, and micro pattern accuracy could be improved by exposure experiment using laser direct imaging system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.132-139
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• 2001

We considered the uniformity of fabricated micromirror arrays by characterizing the fabrication process and calculating the appropriate driving voltages of micromirrors used as virtual photomask in maskless photolithography. The uniformity of the micromirror array in terms of driving voltage and optical characteristics is adversely affected by factors, such as the air gap between the bottom electrode and the mirror plate, the spring shape and the deformation of the mirror plate or torsion spring. The thickness deviation of the photoresist sacrificial layer, the misalignment between mirror plate and bottom electrode, the aluminum deposition condition used to produce the spring and the mirror plate, and initial mirror deflection were identified as key factors. Their importance lies in the fact that they are related to air gap deviations under the mirror plate, asymmetric driving voltages in left and right mirror directions, and the deformation of the Al sring or mirror plate after removal of the sacrificial layer. The plasma ashing conditions used for removing the sacrificial layer also contributed to the deformation of the mirror plate and spring. Driving voltages were calculated for the pixel operation of the micromirror array, and the non-uniform characteristics of fabricated micromirrors were taken into consideration to improve driving performance reliability.

• Design & Manufacturing
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• v.15 no.4
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• pp.57-64
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• 2021

In recent materials industry, researches on the technology to manufacture super hydrophobic surface by effectively controlling the wettability of solid surface are expanding. Research on the fabrication of super hydrophobic surface has been studied not only for basic research but also for self-cleaning, anti-icing, anti-friction, flow resistance reduction in construction, textile, communication, military and aviation fields. A super hydrophobic surface is defined as a surface having a water droplet contact angle of 150 ° or more. The contact angle is determined by the surface energy and is influenced not only by the chemical properties of the surface but also by the rough structure. In this paper, maskless lithography using DMD, electro etching, anodizing and hot embossing are used to make the polymer resin PMMA surface super hydrophobic. In the fabrication of microstructure, DMDs are limited by the spacing of microstructure due to the structural limitations of the mirrors. In order to overcome this, maskless lithography using a transfer mechanism was used in this paper. In this paper, a super hydrophobic surface with micro and nano composite structure was fabricated. And the wettability characteristics of the micro pattern surface were analyzed.

• ETRI Journal
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• v.33 no.4
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• pp.637-640
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• 2011

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip-chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 ${\mu}m$ in one direction.