• 한국정밀공학회지
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• 제23권8호
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• pp.39-46
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• 2006

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin mask layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The mask layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• 한국전기전자재료학회논문지
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• 제18권10호
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• pp.945-949
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• 2005

We have grown GaN layers with in-situ SiN mask by metal organic chemical vapor deposition (MOCVD) and study the physical properties of the GaN layer. We have also fabricate PN junction light emitting diode (LED) to investigate the effect of the SiN mask on its optical property By inserting a SiN mask, (102) the full width at half maximum (FWHM) decreased from 480 arcsec to 409 arcsec and threading dislocation (TD) density decreased from $3.21{\times}10^9\;cm^{-2}$ to $9.7{\times}10^8\;cm^{-2}$. The output power of the LED with a SiN mask increased from 198 mcd to 392 mcd at 20 mA. We have thus shown that the SiN mask improved significantly the physical and optical properties of the GaN layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.284-284
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• 2011

Recently, the increasing degree of device integration in the fabrication of Si semiconductor devices, etching processes of nano-scale materials and high aspect-ratio (HAR) structures become more important. Due to this reason, etch selectivity control during etching of HAR contact holes and trenches is very important. In this study, The etch selectivity and etch rate of TEOS oxide layer using ACL (amorphous carbon layer) mask are investigated various process parameters in CH2F2/C4F8/O2/Ar plasma during etching TEOS oxide layer using ArF/BARC/SiOx/ACL multilevel resist (MLR) structures. The deformation and etch characteristics of TEOS oxide layer using ACL hard mask was investigated in a dual-frequency superimposed capacitively coupled plasma (DFS-CCP) etcher by different fHF/ fLF combinations by varying the CH2F2/ C4F8 gas flow ratio plasmas. The etch characteristics were measured by on scanning electron microscopy (SEM) And X-ray photoelectron spectroscopy (XPS) analyses and Fourier transform infrared spectroscopy (FT-IR). A process window for very high selective etching of TEOS oxide using ACL mask could be determined by controlling the process parameters and in turn degree of polymerization. Mechanisms for high etch selectivity will discussed in detail.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.

• 한국정밀공학회지
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• 제21권8호
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• pp.152-156
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• 2004

A new tool of surface patterning technique for general purpose lithography was developed based on shadow mask method. This paper describes the fabrication of a new type of miniaturized shadow mask. The shadow mask is fabricated by photolithography and etching of 100-mm full wafer. The fabricated shadow mask has over 388 membranes with apertures of micrometer length scale ranging from 1${\mu}{\textrm}{m}$ to 100s ${\mu}{\textrm}{m}$ made on each 2mm${\times}$2mm large low stress silicon nitride membrane. It allows micro scale patterns to be directly deposited on substrate surface through apertures of the membrane. This shadow mask method has much wider choice of deposit materials, and can be applied to wider class of surfaces including chemical functional layer, MEMS/NEMS surfaces, and biosensors.

• 반도체디스플레이기술학회지
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• 제3권2호
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• pp.5-9
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• 2004

Microcircuit fabrication requires precise control of impurities in tiny regions of the silicon. These regions must be interconnected to create components and VLSI circuits. The patterns to define such regions are created by lithographic processes. In order to image features smaller than 70 nm, it is necessary to employ non-optical technology (or next generation lithography: NGL). One such NGL is extreme ultra-violet lithography (EUVL). EUVL transmits the pattern on the wafer surface after reflecting ultra-violet through mask pattern. If particles exist on the blank mask, it can't transmit the accurate pattern on the wafer and decrease the reflectivity. It is important to care the blank mask. We removed the particles on the wafer using focused ion beam (FIB). During removal, FIB beam caused damage the multi layer mask and it decreased the reflectivity. The relationship between particle removal and reflectivity is examined: i) transmission electron microscope (TEM) observation after particle removal, ii) reflectivity simulation. It is found that the image mode of FIB is more effective for particle removal than spot and bar mode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.

• 한국의류학회지
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• 제44권6호
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• pp.1163-1177
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• 2020

The purpose of this study is to figure out the information needed to improve the shape and size suitability of face-applied mask sheets. The study analyzed the shape of the mask sheet from the scanned images of 50 products of 37 domestic brands. In addition, each measurement of 42 mask sheets were compared and analyzed multilaterally with the 3D measurement dimensions of the faces of men and women in their 20s from the 6th SizeKorea data. Analysis on the shapes of mask sheets indicated that domestic commercial mask sheets are mainly made of single or dual sheets, with slits for enhancing fitness to the three-dimensional face. In the dimensional analysis of Korean men, women and mask sheets, most of the lengths of the mask sheets were significantly larger or smaller than the actual faces of men and women. The horizontal length and vertical length of the forehead above the eyes are significantly shorter, thereby requiring adjustments in the dimensions of this area. In order to improve the size suitability of the mask, it is necessary to adjust the dimensions of the problem area according to the research results as well as diversify the dimensions considering the target layer.

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.169-172
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• 2015

Although, there are several research studies on the engineering of the graphene layers using different etching techniques, there is not any comprehensive study on the effects of using different etching masks in the reactive ion etching (RIE) method on the quality and uniformity of the etched graphene films. This study investigated the effects of using polystyrene and conventional photolithography resist as a etching mask on the engineering of the number of graphene layers, using RIE. The effects were studied using Raman spectroscopy. This analysis indicated that the photo-resist mask is better than the polystyrene mask because of its lower post processing effects on the graphene surface during the RIE process. A single layer graphene was achieved from a bi-layer graphene after 3 s of the RIE process using oxygen plasma, and the bi-layer graphene was successfully etched after 6 s of the RIE process. The bilayer etching time was significantly smaller than reported values for graphene flakes in previous research.

• Journal of Information Display
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• 제13권2호
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.