• Industrial Engineering and Management Systems
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• v.8 no.1
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• pp.14-21
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• 2009

We formulate a mathematical model of remanufacturing system as multi-stage reverse Logistics Network Problem (mrLNP) with minimizing the total costs for reverse logistics shipping cost and inventory holding cost at disassembly centers and processing centers over finite planning horizons. For solving this problem, in the 1st and the 2nd stages, we propose a Genetic Algorithm (GA) with priority-based encoding method combined with a new crossover operator called as Weight Mapping Crossover (WMX). A heuristic approach is applied in the 3rd stage where parts are transported from some processing centers to one manufacturer. Computer simulations show the effectiveness and efficiency of our approach. In numerical experiments, the results of the proposed method are better than pnGA (Prufer number-based GA).

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.106-109
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• 2003

This paper presents a hue preserving gamut mapping algorithm for color monitor and printer. The gamuts of monitor and printer are set by the profile of color reproduction media, specified by ICC(International Color Consortium) and provided by vendors, then those gamuts are represented on the CIE xy color space. In case that the color of monitor are located on out-of-gamut of printer, these are clipped on the point of gamut boundary of printer towards a reference white point. On the other hand, colors are in-gamut of printer are unchanged. An image generated by the algorithm keeps a ratio of each pixel of original image. Advantages of the algorithm are easy to implement and fast processing time than other algorithms which involve hue preserving especially in CIELAB color space.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1985-1996
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• 1998

A parallelising algorithm for partitioning and mapping methods of matrix/vector multiplication into linear processor array/VLW simulator is presented in this paper. First we discuss the mapping methods for input matrix or vector into the arbitrarily size of processor arrays. Then, we show partitioning the algorithmss of the large size of computational problem into the size of the processor array. We execute the algorithm on VLIW simuhator and show to effectiviness of algorithm. The result which we achived better parallelising performance on our VLIW simulator dsign than on linear processor array.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.05a
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• pp.105-108
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• 2001

In this paper, the learning algorithm called advanced expanded and truncate algorithm(AETLA) is proposed to training multilayer binary neural network to approximate binary to binary mapping. AETLA used merit of ETL and MTGA learning algorithm. We proposed to new learning algorithm to decrease number of hidden layer. Therefore, learning speed of the proposed AETLA learning algorithm is much faster than other learning algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.5
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• pp.1316-1332
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• 2012

Formation flying is an important technology that enables high cost-effective organization of outer space aircrafts. The ad-hoc wireless network based on direct-sequence ultra-wideband (DS-UWB) techniques is seen as an effective means of establishing wireless communication links between aircrafts. In this paper, based on the theory of matched filter and error bits correction, a hybrid detection algorithm is proposed for realizing multiuser detection (MUD) when the DS-UWB technique is used in the ad-hoc wireless network. The matched filter is used to generate a candidate code set which may contain several error bits. The error bits are then recognized and corrected by an novel error-bit corrector, which consists of two steps: code mapping and clustering. In the former step, based on the modified optimum MUD decision function, a novel mapping function is presented that maps the output candidate codes into a feature space for differentiating the right and wrong codes. In the latter step, the codes are clustered into the right and wrong sets by using the K-means clustering approach. Additionally, in order to prevent some right codes being wrongly classified, a sign judgment method is proposed that reduces the bit error rate (BER) of the system. Compared with the traditional detection approaches, e.g., matched filter, minimum mean square error (MMSE) and decorrelation receiver (DEC), the proposed algorithm can considerably improve the BER performance of the system because of its high probability of recognizing wrong codes. Simulation results show that the proposed algorithm can almost achieve the BER performance of the optimum MUD (OMD). Furthermore, compared with OMD, the proposed algorithm has lower computational complexity, and its BER performance is less sensitive to the number of users.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.68-77
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• 1990

In this paper, a neural patten recognition method for the automatic circuit diagram reading system is proposed. The proposed procedure to recognize a deformed logic symbols is composed of three stages: feature detection, log mapping, and pattern classification. In the feature detection stage, a modified competitive learning algorithm where each pattern has the inhibition weight as well as the activation weight is developed. The global information of hand-written logic symbols is obtained by the feature detection neural network having both the inhibition and activation weights. The obtained global data is then transformed into a log space by the conformal mapping where according to the Schwartz's theory about the human visual signal process-ing, the degree of rotation and the scale change are mapped into the translation change. Logic symbols are finally classified by a three layer perceptron trained by the error back propagation algorithm. The computer simulation demonstrates that the proposed multistage neural network system can recognize well the deformed patterns of hand-written logic circuit diagrams.

• Journal of the Korea Society of Computer and Information
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• v.10 no.2 s.34
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• pp.49-57
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• 2005

In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively

• Journal of Information Technology Services
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• v.22 no.5
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• pp.71-86
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• 2023

Recently, various geographic information systems have been used based on spatial information of geographic information systems. Accordingly, it is essential to produce a large-scale map as a small-scale map for various uses of spatial information. However, maps currently being produced have inconsistencies between data due to production timing and limitations in expression, and productivity efficiency is greatly reduced due to errors in products or overlapping processes. In order to improve this, various efforts are being made, such as publishing research and reports for automating domestic mapping, but because there is no specific result, it relies on editors to make maps. This is mainly done by hand, so the time required for mapping is excessive, and quality control for each producer is different. In order to solve these problems, technology that can be automatically produced through computer programs is needed. Research has been conducted to apply the rule base to geometric generalization. The algorithm tolerance setting applied to rule-based modeling is a factor that greatly affects the result, and the level of the result changes accordingly. In this paper, we tried to study the effectiveness of mapping according to tolerance setting. To this end, the utility was verified by comparing it with a manually produced map. In addition, the original data and reduction rate were analyzed by applying generalization algorithms and tolerance values. Although there are some differences by region, it was confirmed that the complexity decreased on average. Through this, it is expected to contribute to the use of spatial information-based services by improving tolerances suitable for small-scale mapping regulations in order to secure spatial information data that guarantees consistency and accuracy.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.1
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• pp.26-30
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• 2008

It is important matter that inflect well allocated frequency resource in cellular network and is still more serious element in environment that provide multimedia services. This paper describes model and algorithm that increase two elements that is frequency allocation and job scheduling that consider multimedia service traffic special quality by emphasis that do mapping present in CDMA cellular system. We proposed the model cpomposed three parts (channel allocation algorithm, mapping algorithm using genetic algorithm and scheduling algorithm) and simulation results.