• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• Journal of Magnetics
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• 제7권3호
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 춘계학술대회 논문집
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• pp.110-110
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• 2009

최근 차세대 비휘발성 메모리(NVM) 기술은 메모리의 성능과 기존의 한계점을 효과적으로 극복하며 활발한 연구를 통해 비약적으로 발전하고 있으며 특히, phase-change random access memory (PRAM)은 ferroelectric random access memory (FeRAM)과 magneto-resistive random access memory (MRAM)과 같은 다른 NVM 소자와 비교하여 기존의 DRAM과 구조적으로 비슷하고 상용화가 빠르게 진행될 수 있을 것으로 예상되는 바, PRAM에 사용되는 상변화 물질의 식각을 수행하고 X-ray photoelectron spectroscopy (XPS)를 통해 표면의 열화현상을 관찰하였다.

• 정보과학회 논문지
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• 제42권3호
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• pp.379-389
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• 2015

Phase Change Memory (PCM 또는 PRAM), Magneto Resistive RAM (MRAM)과 같은 차세대 비휘발성 메모리가 등장하면서, Dynamic Random-Access Memory (DRAM)을 PRAM으로 대체하는 연구가 활발히 진행되고 있다. 본 논문에서는 PRAM을 메인 메모리로 사용하는 시스템에서 지금까지 널리 사용되고 있는 기존의 조인 알고리즘(블록 네스티드 조인, 소트-머지 조인, 그레이스 해시 조인, 하이브리드 해시 조인)들을 사용했을 때 발생하는 내구성과 성능 문제를 비교, 분석한다. 본 연구의 실험결과에 의하면 기존의 조인 알고리즘들을 PRAM에 맞게 재설계해야 하는 필요성이 제기되었다. 특히, 본 연구는 조인 알고리즘들을 PRAM에 적용했을 때 발생하는 이슈들을 과학적으로 규명한 첫 시도이다. 그리고 기존의 조인 알고리즘들을 PRAM에 적용했을 때 발생하는 내구성과 성능을 비교하기 위한 PRAM 기반의 시스템을 모델링하고 시뮬레이터를 구현한 것에 연구의 의의를 둘 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.110-116
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• 2004

We propose a novel sensing scheme, which operates by sensing the difference in voltage between a memory cell and a reference cell for a magneto-resistive random access memory (MRAM). A new midpoint-reference generation circuit is adopted for the reference cell to improve the sensing margin and to guarantee correct operation of sensing circuit for wide range of tunnel magneto resistance (TMR) voltages. In this scheme, the output voltage of the reference cell becomes nearly the midpoint between the cell voltages of high and low states even if the voltage across the magnetic tunnel junction (MTJ) varies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• 대한전자공학회논문지SD
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• 제41권8호
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• pp.105-113
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• 2004

MRAM (Magneto-resistive Random Access Memory)은 자성체의 스핀 방향을 정보원으로 하는 비휘발성 메모리로 magneto-resistance 물질을 정보 저장 소자로 사용한다. 본 논문에서는 MRAM 시뮬레이션시 MTJ (Magnetic Tunneling Junction)의 hysteretic 특성, asteroid 특성, R-V 특성을 HSPICE에서 재현할 수 있는 새로운 macro-model을 제안하고 HSPICE에 적용하여 그 정확도를 검증하였다. 또한 종래의 reference cell 회로에 비하여 정확한 중간 저항 값을 유지하는 새로운 reference cell 회로를 제안하고 이를 본 논문에서 제안한 macro-model을 이용하여 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.356.2-356.2
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• 2014

Spin Transfer Torque (STT) is of great interest in data writing scheme for the Magneto-resistive Random Access Memory (MRAM) using Magnetic Tunnel Junction (MTJ). Scalability for high density memory requires ferromagnetic electrodes having the perpendicular magnetic easy axis. We investigated CoZr as the ferromagnetic electrode. It is observed that interfacial magnetic anisotropy is preferred perpendicular to the plane with thickness dependence on the interfaces with Pt layer. The anisotropy energy (Ku) with thickness dependence shows a change of magnetic-easy-axis direction from perpendicular to in-plane around 1.2 nm of CoZr. The interfacial anisotropy (Ki) as the directly related parameters to switching and thermal stability, are estimated as $1.64erg/cm^2$ from CoZr/Pt multilayered system.