• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.51-54
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• 1998

In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.175-184
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• 2016

In this paper, we propose the method to measure the capacitances using not LCR meter but capacitance to voltage(C/V) conversion. And we design the analog MUX circuits that convert 192 channels to 6 MUX channels in order to implement the diagnosis of multi-channel ultrasonic probe. This paper derives the conversion function that converts the digital voltage of each MUX channel to the capacitance using the least squares method because the circuit characteristics that convert the voltage of each MUX channel to the capacitance are different. The developed prototype illustrates the performance test results that the measure times are measured by within 4sec and the measure error rates of maximum, minimum, and average values are within 5% in terms of the repeated measurements of all 192 channels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.155-159
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• 2017

The analog-to-digital converter (ADC) is an important component in various fields of sensor signal processing. This paper presents an expandable flash analog-to-digital converter (E-flash ADC) for sensor signal processing using a comparator, a subtractor, and a multiplexer (MUX). The E-flash ADC was simulated and designed in $0.35-{\mu}m$ standard complementary metal-oxide semiconductor (CMOS) technology. For operating the E-flash ADC, input voltage is supplied to the inputs of the comparator and subtractor. When the input voltage is lower than the reference voltage, it is outputted through the MUX in its original form. When it is higher than the reference voltage, the reference voltage is subtracted from the input value and the resulting voltage is outputted through the MUX. Operation of the MUX is determined by the output of the comparator. Further, the output of the comparator is a digital code. The E-flash ADC can be expanded easily.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.996-1005
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• 2001

본 논문에서는 ASIC 벤더의 셀 라이브러리와 MUX-based FPGA에 있는 고정된 입력을 갖는 연결구조의 수를 최소화하는 하드웨어 할당 알고리듬을 제안한다. 제안된 할당 알고리듬은 연산자간을 연결하는 신호선이 반복적으로 이용되어 연결 신호선 수가 최소가 될 수 있도록 연산자를 할당한다. 연결 구조를 고려한 이분할 그래프에 가중치를 설정하고 변수와 레지스터간의 최대 가중치 매칭을 구함으로써 레지스터 할당을 수행한다. 또한 연결구조에 대한 멀티플렉서의 중복 입력을 제거하고 연산자에 연결된 멀티플렉서간의 입력을 교환하는 입력 정렬 과정으로 연결구조를 최소화한다. 벤치마크 실험을 통하여 제안된 알고리즘의 효용성을 보인다.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.237-240
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• 2001

Dense Wavelength division multiplexing(DWDM) lightwave system requires multiplexer, demultiplexer and optical filter. In this paper, thus, we propose the Add-Drop Mux/Demux based on a Mach-Zehnder interferometer(MZI) with fiber Bragg grating(FBG). The Add-Drop Mux/Demux using FBG and MZI is able to minimize system and reduce weight. We also analyze output characteristics of Add-Drop Mux/Demux and present the optimum design data through the computer simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.85-91
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• 1993

In this paper, we propose the test pattern generation algorithm of the embedded faulty MUX for the prevention of misdiagnosis of digital systems. When the system is partitioned with a large number of functional blocks, if the faults are exsisted in a embedded MUX then it can not diagnose the wanted observation of functional block. The proposed test pattern generstion algorithm can apply the MUXs that designd 2-level and multi-level both. Fault coverage becomes 100% and so it is no necessary of the additional fault simulation and the proposed algorithm that have the regulary and easily generated 2d test patterns. And we confirmed that the reduction of test cost becomes 85%, compared with the conventional segmentation testing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.22-29
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• 2007

A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s.