A Parallel Test Structure for eDRAM-based Tightly Coupled Memory in SoCs (시스템 온 칩 내 eDRAM을 사용한 Tightly Coupled Memory의 병렬 테스트 구조)
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- The Journal of Korea Institute of Information, Electronics, and Communication Technology
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- v.4 no.3
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- pp.209-216
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- 2011