• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.575-581
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• 2013

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1136-1139
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• 2000

The paper describes a new and rigorous mathematical model for the rotor field oriented system with induction motor which uses the estimated speed and rotor flux based on a Model Reference Adaptive System, as well as the real-time approach. The estimated speed and rotor flux is used for the speed and flux feedback control. The stability and the convergence of the estimator are improved on the basis of hyperstability theory for non-linear systems. The real-time controller and estimator are implemented with a sampling period of $926{\mu}s$ using a dual TMS320C44 floating-point digital signal processor. The validity of the proposed method is verified by simulation, and also, the sensorless control was tested on the propulsion system simulator, used for the development of Korean High-Speed Railway Train (KHSRT) [5].

• Particle and aerosol research
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• v.9 no.2
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• pp.51-57
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• 2013

A graphene(GR)-$TiO_2$ composite was synthesized from colloidal mixture of graphene oxide(GO) nanosheets and $TiO_2$ nanoparticles by an aerosol assisted self-assembly. The morphology, specific surface area and pore size of asprepared GR-$TiO_2$ composite were characterized by FE-SEM, BET, and BJH respectively. The shape of GR-$TiO_2$ composite was spherical. The average particle size was 0.5-1 ${\mu}m$ in diameter and the pore diameter ranged 20-50 nm. Photovoltaic characteristics of a mixture of the GR-$TiO_2$ and $TiO_2$ nanoparticles were measured by a solar simulator under simulated solar light. The highest photoelectric conversion efficiency of the mixture photoanode was 5.1%, which was higher than that of $TiO_2$ photoanode.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of the Korean Ceramic Society
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• v.52 no.5
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• pp.380-383
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• 2015

We prepared the $TiO_2$ layer with 0 ~ 4 wt% of polystyrene (PS) beads having a radius of 250 nm to increase the dye adsorption and energy conversion efficiency (ECE) of a dye sensitized solar cell (DSSC). Then, we fabricated DSSCs using $0.45cm^2$ active area. FE-SEM was used to characterize the microstructure consisting of $TiO_2$ layer and PS beads. UV-VIS-NIR was used to determine the optical absorbance of working electrodes (WEs). Solar simulator and potentiostat were used to determine the photovoltaic properties. We observed that pores having a radius of 250 nm were formed with the density of $0.15ea/{\mu}m^2$ in $TiO_2$ layers after conducting the sintering process. The absorbance in visible light regime was found to increase with the increase in the amount of PS beads. The ECE increased from 4.66% to 5.25% when the amount of PS beads was increased from 0 to 4 wt%. This is because the pores of PS beads increased the adsorption of dye. Our results indicate that the ECE of the DSSCs can be enhanced by the addition of an appropriate amount of PS beads into $TiO_2$ layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.225-225
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• 2010

In this study, the optimum structure of a magnetic thin film inductor was designed for application of DC-DC converters. The $Ni_{81}Fe_{19}$ (at%) alloy was selected as a high-frequency($\geq$ MHz) magnetic thin film core material and deposited on various substrates (bare Si, $SiO_2$ coated Si) using a high vacuum RF magnetron sputtering system. As-deposited NiFe thin films show similar magnetic properties compared to bulk NiFe alloys, indicating that they have a good film quality. The optimum design of solenoid-type magnetic thin film inductors was performed utilizing a Maxwell computer simulator (Ansoft HFSS V7.0 for PC) and parameters obtained from the magnetic properties of magnetic core materials selected. The high-frequency characteristics of the inductance(L) and quality factor(Q) obtained for the designed inductors through simulation agreed well with those obtained by theoretical calculations, confirming that the simulated result is realistic. The optimum structure of high-performance ($Q{\geq}60$, $L\;=\;1{\mu}H$, efficiency${\geq}90%$), high-frequency (${\geq}5MHz$), and solenoid-type magnetic thin film inductors was designed successfully.

• Journal of radiological science and technology
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• v.44 no.2
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• pp.123-131
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• 2021

In this study, safety education contents for medical radiation workers were produced based on Mixed Reality(MR). Currently, safety training for radiation workers is based on theory. This is insufficient in terms of worker satisfaction and efficiency. To address this, we created ICT(Information and Communication Technologies)-based MR radiation worker safety education content. The expected effect of Mixed Reality worker safety education content is that education is possible without space and time constraints, realistic education is possible without on-site training, and interaction between images is possible through reality-based 3D images, enabling self-directed learning Is that. In addition, learning in a virtual space expressed through HMD(Head Mounted Display) is expected to make education more enjoyable and increase concentration, thereby increasing the efficiency of education. A quantitative evaluation was conducted by an accredited institution and a qualitative evaluation was performed on users, which received excellent evaluation. The MR safety education conducted in this study is expected to be of great help to the education of medical radiation workers, and is expected to develop into a new educational paradigm as online education in accordance with Corona 19 progresses.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.722-725
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• 2003

In AC plasma display, it is very important to quantify the wall voltage induced by the wall charge accumulated on the dielectric surface. If we know the quantities of the wall voltage in each period of every sequence; reset period, address period and sustain period, then it helps us to design the optimal driving waveform for high efficiency plasma display. We develop a new method to measure the wall voltage with VDS (Versatile Driving Simulator) system. From this method the wall voltage induced by a wall charge profiles just after the reset discharge of every cells in plasma display panel can be investigated and analyzed successfully. It is noted that the wall voltage profiles are influenced by the space charge and then they are stabilized as time goes by. It is also noted that both the remaining wall charge at the previous sequence and space charges contribute to wall voltage quantities just after the reset discharge. It is noted that the wall charges contribute dominantly after a few hundreds microseconds, while the space charges have been decayed within 100 ${\mu}s$ just after the reset discharge.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.66-76
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• 1998

In this paper, we implement a buffer capable of handling short loops references to statistically lower the miss rate of variable-length instructions stored in the instruction buffer. MAU(Mark Appending Unit) takes the instructions as they are fetched from external memory, performs some initial decode operations and stores the results of the decode in the buffer for reducing multiple decodes when instructions are executed repeatedly such as in a loop. It includes a decision block of whether hit or not for effectively processing branch instructions Each module of the proposed architecture of processing variable-length instruction is described in VHDL structurally and behaviorally and whether it is working well or not is checked on V-System simulator of Model Technology Inc. We synthesized and simulated the architecture using an ASIC Synthesizer tool with 0.6$\mu\textrm{m}$ 5-Volt CMOS COMPASS library. Operation speed is up to 140MHz. The architecture includes about 17,000 gates.