• Journal of IKEEE
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• v.25 no.1
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• pp.1-9
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• 2021

In this paper, a 4H-SiC UMOSFET was studied which is suitable for high voltage and high current applications. In general, SiO2 is a material most commonly used as a gate dielectric material in SiC MOSFETs. However, since the dielectric constant value is 2.5 times lower than 4H-SiC, it suffers a high electric field and has poor characteristics in the SiO2/SiC junction. Therefore, the static characteristics of a device with high-k material as a gate dielectric and a device with SiO2 were compared using TCAD simulation. The results show BV decreased, VTH decreased, gm increased, and Ron decreased. Especially when the temperature is 300K, the Ron of Al2O3 and HfO2 decreases by 66.29% and 69.49%. and at 600K, Ron decreases by 39.71% and 49.88%, respectively. Thus, Al2O3 and HfO2 are suitable as gate dielectric materials for high voltage SiC MOSFET.

• Journal of the Korean Magnetics Society
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• v.15 no.5
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• pp.287-291
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• 2005

We have investigated and tried to improve the characteristics of the thin $HfO_2$ layer deposited by ALD for fabricating a MOSFET device where the $HfO_2$ film worked as the gate dielectric. The substrate of MOSFET device is p-type (100) silicon wafer over which the $HfO_2$ dielectric layer with thickness of $5\~6\;nm$ has been deposited. Then the $HfO_2$ film was annealed with $1\~20\;atm\;H_2$ gas and subsequently aluminum electrodes was made so that the active area was $5{\times}10^{-5}\;cm^2$. We have found out that the drain current and transconductance increased by $5\~10\%$ when the $H_2$ gas pressure was 20 atm, which significantly contributed to the reliable operation of the high-density MOSFET devices.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.3
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• pp.101-105
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• 2004

The efficient power MOSFET inverter applied for a simple and low cost power supply is proposed for driving the dielectric barrier discharge (DBD) lamp load. For decades, the DBD phenomenon has been used for ozone gas production in industry. In this research, the ultraviolet and visible light sources utilizing the DBD lamp is considered as the load for solid-state high frequency power supply. It is found that the simple voltage-source single-ended quasi-resonant ZVS inverter with only one active power switch could effectively drive this load with the output power up to 700 W. The pulse density modulation based control scheme for the single-ended quasi-resonant ZVS inverter using a low voltage and high current power MOSFET switching device is proposed to provide a linear power regulation characteristic in the wide range 0-100％ of the full power as compared with the conventional control based Royer type parallel resonant inverter type power supplies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.24-31
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• 2003

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.20-23
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• 2000

We have investigated a process for the preparation of high-quality tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$) via the N $H_3$ annealing of 7$_{a2}$ $O_{5}$, for use in gate dielectric applications. Compared with tantalum oxide (7$_{a2}$ $O_{5}$), a significant improvement in the dielectric constant was obtained by the N $H_3$ treatment. In addition, light reoxidation in a wet ambient at 45$0^{\circ}C$ resulted in a significantly reduced leakage current. We confirmed nitrogen incorporation in the tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$ by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness as thin as 1.6nm and a leakage current of less than 10mA/$\textrm{cm}^2$ at 1.5V..5V..5V..5V..5V..5V.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.154-155
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• 2012

In this work, we report the comprehensive study of performance enhancement of InGaAs n-MOSFET by plasma $PH_3$ p assivation. The calibrated plasma $PH_3$ passivation of the InGaA ssurface before CVD high-k dielectric deposition significantly improves interface quality, resulting in suppressed frequency dispersion in C-V, increase in drive-current with high electron mobility, and excellent thermal stability.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.173-179
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• 2023

This paper analyzes the time-dependent dielectric breakdown(TDDB) degradation mechanism for each stress region of Peri devices manufactured by 4th generation VNAND process, and presents a complementary lifetime prediction model that improves speed and accuracy in a wider reliability evaluation region compared to the conventional model presented. SiON dielectric nMOSFETs were measured 10 times each under 5 constant voltage stress(CVS) conditions. The analysis of stress-induced leakage current(SILC) confirmed the significance of the field-based degradation mechanism in the low electric field region and the current-based degradation mechanism in the high field region. Time-to-failure(TF) was extracted from Weibull distribution to ascertain the lifetime prediction limitations of the conventional E-model and 1/E-model, and a parallel complementary model including both electric field and current based degradation mechanisms was proposed by extracting and combining the thermal bond breakage rate constant(k) of each model. Finally, when predicting the lifetime of the measured TDDB data, the proposed complementary model predicts lifetime faster and more accurately, even in the wider electric field region, compared to the conventional E-model and 1/E-model.