• 제목/요약/키워드: MOSFET Level 3 Model

검색결과 5건 처리시간 0.021초

NVSM 회로설계를 위한 SONOSFET SPICE 파라미터의 최적화 (The Optimization of SONOSFET SPICE Parameters for NVSM Circuit Design)

  • 김병철;김주연;김선주;서광열
    • 한국전기전자재료학회논문지
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    • 제11권5호
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    • pp.347-352
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    • 1998
  • In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

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Si MOSFET과 GaN FET Power System 성능 비교 평가 (Comparative Performance Evaluation of Si MOSFET and GaN FET Power System)

  • 안정훈;이병국;김종수
    • 전력전자학회논문지
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    • 제19권3호
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    • pp.283-289
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    • 2014
  • This paper carries out a series of analysis of power system using Gallium Nitride (GaN) FET which has wide band gap (WBG) characteristics comparing to conventional Si MOSFET-used power system. At first, for comparison of each semiconductor device, the switching-transient parameter is quantitatively extracted from released information of GaN FET. And GaN FET model which reflect this dynamic property is configured. By using this model, the performance of GaN FET is analyzed comparing to Si MOSFET. Also, in order to enable a representative assessment on the power system level, Si MOSFET and GaN FET are applied to the most common structure of power system, full-bridge, and each power systems are compared based on various criteria, such as performance, efficiency and power density. The entire process is verified with the aid of mathematical analysis and simulation.

CMOS Current Sum/Subtract Circuit

  • Parnklang, Jirawath;Manasaprom, Ampual
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2001년도 ICCAS
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    • pp.108.6-108
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    • 2001
  • The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

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MOS소자 반전층의 전자이동도에 대한 해석적 모델 (An analytical model for inversion layer electron mobility in MOSFET)

  • 신형순
    • E2M - 전기 전자와 첨단 소재
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    • 제9권2호
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    • pp.174-179
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    • 1996
  • We present a new physically based analytical equation for electron effective mobility in MOS inversion layers. The new semi-empirical model is accounting expicitly for surface roughness scattering and screened Coulomb scattering in addition to phonon scattering. This model shows excellent agreement with experimentally measured effective mobility data from three different published sources for a wide range of effective transverse field, channel doping and temperature. By accounting for screened Coulomb scattering due to doping impurities in the channel, our model describes very well the roll-off of effective mobility in the low field (threshold) region for a wide range of channel doping level (Na=3.0*10$^{14}$ - 2.8*10$^{18}$ cm$^{-3}$ ).

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An Analytical Model of the First Eigen Energy Level for MOSFETs Having Ultrathin Gate Oxides

  • Yadav, B. Pavan Kumar;Dutta, Aloke K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권3호
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    • pp.203-212
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    • 2010
  • In this paper, we present an analytical model for the first eigen energy level ($E_0$) of the carriers in the inversion layer in present generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. Commonly used approaches to evaluate $E_0$ make either or both of the following two assumptions: one is that the barrier height at the oxide-semiconductor interface is infinite (with the consequence that the wave function at this interface is forced to zero), while the other is the triangular potential well approximation within the semiconductor (resulting in a constant electric field throughout the semiconductor, equal to the surface electric field). Obviously, both these assumptions are wrong, however, in order to correctly account for these two effects, one needs to solve Schrodinger and Poisson equations simultaneously, with the approach turning numerical and computationally intensive. In this work, we have derived a closed-form analytical expression for $E_0$, with due considerations for both the assumptions mentioned above. In order to account for the finite barrier height at the oxide-semiconductor interface, we have used the asymptotic approximations of the Airy function integrals to find the wave functions at the oxide and the semiconductor. Then, by applying the boundary condition at the oxide-semiconductor interface, we developed the model for $E_0$. With regard to the second assumption, we proposed the inclusion of a fitting parameter in the wellknown effective electric field model. The results matched very well with those obtained from Li's model. Another unique contribution of this work is to explicitly account for the finite oxide-semiconductor barrier height, which none of the reported works considered.