• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).

• Journal of the Institute of Convergence Signal Processing
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• v.25 no.1
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• pp.46-51
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• 2024

Drone was first used for military purposes but as the range of use has recently expanded. It is being widely used in various industrial fields such as agriculture, service, logistics, and leisure. Lithium polymer batteries are lightweight and highly efficient, so they are mainly used as power supplies for drones. Accordingly, the need for lightweight and high energy density lithium polymer batteries has increased in order to supply stable power to drone. However, lithium polymer batteries can lead to ignition and explosion due to overcharging, short circuit, etc., so they must be used with a protective circuit installed. The protection circuit consists of a protection IC that monitors the voltage of the lithium polymer battery and a dual N-channel MOSFET that acts as a switch in case of overcharge and overdischarge. Therefore, this paper was implemented in one package form using a battery protection IC and a MOSFET semiconductor die chip serving as a switch. When implemented as a one chip package IC, at least 67% of savings compared to existing parts can be achieved.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.196-198
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• 2020

본 논문은 SiC MOSFET의 단락 검출을 위한 고정밀 Rogowski 코일 회로 설계 방법을 제안한다. 설계 방법을 제안하기 위해 먼저 Rogowski 코일의 기본 구성인 적분기를 실제 시스템 요구 사양에 맞추어 설계한다. 설계한 회로의 성능 확인을 위하여 DPT (double pulse test)를 실시하며, test 결과 분석을 통해 문제점을 파악하고 전류 센싱 정밀도 향상을 위해 입출력 필터 설계 및 Rogowski 코일 턴 수를 변경한다. 변경한 각 조건들에 대하여 DPT를 진행하고 각 test 결과를 기반으로 Rogowski 코일 회로 설계 방안을 제안한다.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.33-39
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• 2014

In this paper, a new on-chip aging sensing circuit based on flip-flops is proposed to detect a circuit failure of MOSFET digital circuits casued by aging phenomenon such as HCI and BTI. The proposed circuit uses timing windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur. The generated bits can apply to an adaptive self-tuning method for reliable system design as control signals. The aging sensor circuit has been implemented using 0.11um CMOS technology and evaluated by $4{\times}4$ multiplier with power gating structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.719-726
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• 2008

In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.225-232
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• 2009

An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DG-MOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.