• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2079-2081
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• 2003

현재 산업화 사회가 가속됨에 따라 인체에 유해한 물질들이 발생한다. 그 중에서 VOC(Volatile Organic Component)는 인체에 치명적인 해를 일으키는 물질이다. 본 논문은 MOS(Metal Oxide Semiconductor) 센서를 이용하여 인체에 치명적인 유해 물질인 VOC를 측정하였다. 현재 VOC의 측정은 GC(Gas Chromatograph)를 이용하는데 이는 측정 시간이 길며 숙련된 측정자에 의해서만 측정이 가능하고 그 분석이 가능하다. 그러나 MOS 센서를 이용하면 숙련되지 않은 측정자도 측정이 가능하며 인공신경망을 이용하여 그 분석을 함으로서 누구나 쉽게 분석이 가능하고 실시간으로 측정이 가능하다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.79-79
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• 2003

최근 CMOS(Complementary Metal Oxide Semiconductor) 능동소자에 사용되는 MOS-FET (Metal Oxide Semiconductror Field Effect Transitror)의 전체적인 크기 감소추세에 따라 금속 전극과 반도체 사이의 절연층 두께 감소가 요구되고 있다. 현재 보편적으로 사용되고 있는 SiO$_2$층은 두께 감소에 따른 터널링 전류의 증가로 더 이상의 두께 감소를 기대하기 어려운 상태이다. 이러한 배경에서 최근 터널링 전류를 충분히 감소시키면서 요구되는 절연특성을 얻을 수 있는 새로운 고유전 물질 (high-k dielectric material)에 대한 연구가 이루어지고 있다. 현재까지 연구되어온 고유전 물질 중, 고유전 상수, 큰 밴드갭, Si과의 열적 안정성을 갖는 물질로 ZrO$_2$가 주목을 받고 있다. 본 연구에서는 Metal Organic Molecular Beam Epitaxy (MOMBE) 방법을 이용한 ZrO$_2$ 층의 성장조건 및 특성을 평가하고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.206.1-206.1
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• 2015

최근에 금속산화물을 증착하는 방법으로 용액공정이 주목 받고 있다. 용액 공정은 대기압에서 매우 간단한 방법으로 복잡한 공정과정을 요구하지 않기 때문에 박막을 경제적으로 간단하게 형성할 수 있다. 하지만 용액공정을 통해 형성한 박막에는 소자의 특성을 열화 시키는 solvent와 탄소계열의 불순물을 많이 포함하고 있어 고온의 열처리가 필수적이다. 박막의 품질을 향상시키기 위해서 다양한 열처리 방법들이 이용되고 있으며, 일반적인 열처리 방법으로는 furnace를 이용한 conventional thermal annealing (CTA)이 많이 이용되고 있다. 하지만, 최근에는 microwave를 이용한 공정이 주목 받고 있다. Microwave energy는 CTA보다 효과적으로 비교적 낮은 온도에서 높은 열처리 효과를 나타낸다. 본 실험은 n-type Silicon 기판에 solution-ZrO2 산화막을 형성 후, oven baking을 한 뒤, CTA와 microwave를 이용하여 solvent와 불순물을 제거 하였다. 전기적 특성을 확인하기 위해 solution ZrO2 산화막 위에 E-beam evaporator를 이용해 Ti 금속 전극을 증착하여 Metal-Oxide-Semiconductor (MOS) capacitor를 제작하였다. 다음으로, PRECISION SEMICONDUCTOR PARAMETER ANALYZER (4156B)를 이용하여, capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 비교하였다. 다음으로, CTA를 통하여 제작한 소자와 전기적 특성을 비교하였다. 그 결과, Microwave irradiation으로 열처리한 MOS capacitor 소자에서 capacitance 값과 flat band voltage, hysteresis 등이 개선되는 효과를 확인하였다. Microwave irradiation 열처리는 100oC 미만의 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 ZrO2 용액의 불순물과 solvent를 낮은 온도에서 제거하여 고품질 박막 형성에 매우 효과적이라는 것을 나타낸다. 따라서, microwave irradiation 열처리 방법은 비정질 산화막이 포함되는 박막 transistor 소자 제작에 대하여 결정적인 열처리 방법이 될 것으로 기대한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.76-83
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• 1985

Mo2N/Mo double layer which is to be used for gate of the RMOS (refractory metal oxide semiconductor) and interconnection material has been formed by means of low temperature r.f. reactive sputtering in Ar and N2 mixture. The sheet .esistance of 1 000$\AA$Mo2 N/4000$\AA$Mofilm was about 1.20-1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film. The workfunction difference naE between MO2N/MO layer and (100) p-Si with 6-9 ohm'cm resistivity obtained from C-V plots was about -0.30ev, and the fixed charge density Qss/q in the oxide was about 2. Ix1011/cm2. To evaluate the signal transfer delay time per inverter stage, an integrated ring oscillator circuit consisting of 45-stage inverters was fabricated using the polysilicon gate NMOS process. The signal transfer delay time per inverter stage obtained in this experiment was about 0.8 nsec

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.77-82
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• 1996

The breakdown characteristics of metal-oxide-semiconductor(MOS) capacitors fabricated by Al, polysilicon, and tungsten polycide gate electrodes onto gate oxide was evaluated by time zero dielectric breakdwon (TZDB). The average breakdown field of the gate oxide with tungsten polycide electride was lower than that of the polysilicon electrode. The B model (1~8MV/cm) failure of the gate oxide with tungsten polycide electrode was increased with increasing annealing temperature in the dry $O_{2}$ ambient. This is attributed ot fluorine and tungsten diffusion from thungsten silicide film into the gate oxide, and stress increase of tungsten polcide after annealing treatment.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.188-198
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• 1993

We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.44-50
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• 2001

Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.