• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• The Journal of the Korea Contents Association
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• v.8 no.6
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• pp.74-81
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• 2008

Protein interaction network contains a small number of highly connected protein, denoted hub and many destitutely connected proteins. Recently, several studies described that a hub protein is more likely to be essential than a non-hub protein. This phenomenon called as a centrality-lethality rule. This nile is widely credited to exhibit the importance of hub proteins in the complex network and the significance of network architecture as well. To confirm whether the rule is accurate, we Investigated all protein interaction DBs of yeast in the public sites such as Uetz, Ito, MIPS, DIP, SGB, and BioGRID. Interestingly, the protein network shows that the rule is correct in lower scale DBs (e.g., Uetz, Ito, and DIP) but is not correct in higher scale DBs (e.g., SGD and BioGRID). We are now analyzing the features of networks obtained from the SGD and BioGRD and comparing those of network from the DIP.

• The Journal of the Korea Contents Association
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• v.9 no.5
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• pp.332-336
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• 2009

Functional prediction of unannotated proteins is one of the most important tasks in yeast genomics. Analysis of a protein-protein interaction network leads to a better understanding of the functions of unannotated proteins. A number of researches have been performed for the functional prediction of unannotated proteins from a protein-protein interaction network. A chi-square method is one of the existing methods for the functional prediction of unannotated proteins from a protein-protein interaction network. But, the method does not consider the topology of network. In this paper, we propose a novel method that is able to predict specific molecular functions for unannotated proteins from a protein-protein interaction network. To do this, we investigated all protein interaction DBs of yeast in the public sites such as MIPS, DIP, and SGD. For the prediction of unannotated proteins, we employed a modified chi-square measure based on neighborhood counting and we assess the prediction accuracy of protein function from a protein-protein interaction network.

• The Journal of the Korea Contents Association
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• v.8 no.1
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• pp.259-271
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• 2008

We propose a protein function finding algorithm that is able to predict specific molecular function for unannotated proteins through domain analysis from protein-protein network. To do this, we first construct protein-protein interaction(PPI) network in Saccharomyces cerevisiae from MIPS databases. The PPI network(proteins; 3,637, interactions; 10,391) shows the characteristics of a scale-free network and a hierarchical network that proteins with a number of interactions occur in small and the inherent modularity of protein clusters. Protein-protein interaction databases obtained from a Y2H(Yeast Two Hybrid) screen or a composite data set include random false positives. To filter the database, we reconstruct the PPI networks based on the cellular localization. And then we analyze Hub proteins and the network structure in the reconstructed network and define structural modules from the network. We analyze protein domains from the structural modules and derive functional modules from them. From the derived functional modules with high certainty, we find tentative functions for unannotated proteins.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.45-51
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• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.202-208
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• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.