• The Journal of Korean Association of Computer Education
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• v.16 no.3
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• pp.99-105
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• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.9-12
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• 2001

본 논문에서는 유럽 통신 표준화기구인 ETSI 의 SMGll에서 채택된 GSM Full Rate(FR) 보코더 알고리wma[1]을 Teak DSP Core를 이용하여 실시간 구현하였다. GSM FR 보코더는 유럽에서 사용하는 통신 시스템인 GSM 의 full-rate Traffic Channel(TCH)의 표준 코덱[2]으로서 GSM HR, GSM EFR GSM AMR과 더불어 모뎀칩 내에 장착되는 필수적인 음성 서비스이다. 구현된 GSM FR는 13.05kbps의 비트율을 가지고 있으며, 인코더와 디코더 기능 외에 voice activity detection(VAD)[3]블록과 DTX[4]블록 등의 부가 기능도 구현되어 있다. 구현에 사용된 Teak[5]는 DSP Group 의 16bit고정 소수점 DSP core로서 최대 140MIPS 의 성능을 낼 수 있고 400bits ALU 와 두개의 MAC 이 장착되어 있어 음성 및 채널 부호화기의 실시간 처리에 최적화 되어있다. 구현된 GSM FR 은 인코더와 디코더 부분이 각각 약 235 MIPS 및 1.19MIPS 의 복잡도를 나타내며, 사용된 메모리는 프로그램 ROM 3.9K words, 데이터 ROM(table) 396 words 및 RAM 932words이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1370-1376
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• 2008

Recently years There are numerous music contents on the internet and it can easily be used without any authority. because of this, casualties of music contents has been increased and music market has collapsed. Therefore Record Copyright Association protection law has revised and using music contents are being managed by copyright holders group from this year. It is one of ways to protect their contents copyright. So on this paper Internet Radio solution is provided to solve the problem between copyright holders and someone wants to use their contents and to make a part of new market on the music contents.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Smart Media Journal
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• v.3 no.4
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• pp.9-15
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• 2014

A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

• The Journal of the Acoustical Society of Korea
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• v.20 no.7
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• pp.63-68
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• 2001

This paper describes the details of ITU-T SGIS G.729A speech coder implementation using ARM9 Thumb/sup R/ processor core and various techniques used in the optimization process. ITU-T G.729 speech coder is the standard of the toll quality 8 kbit/s speech coding. The input to the speech encoder is assumed to be a 16 bits PCM signal at a sampling rate of 8000 samples per second. G.729A is reduced complexity version of the G.729 coder. This version is bit stream interoperable with the full version. The implemented coder requires 34.8 MIPS for the encoder and 8.1 MIPS for the decoder, 36.5 kBytes of program ROM and 6.3 kBytes of data RAM, respectively. The implemented coder is tested against the set of 9 test vectors provided by ITU-T for bit exact implementation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.91-98
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• 2008

Domestic standard for Korean T-DMB includes MPEG-4 BSAC (Bit Sliced Arithmetic Coding) audio coding that has been established in 2003. This paper presents an implementation and optimization of MPEG-4 BSAC Audio Decoder on ARM926EJ-S processor. Tools and modules of the BSAC audio decoder were implemented with 32-bit fixed point operations. Further optimization was accomplished using ARM926EJ-S Inline Assembly. The optimization was based on the total number of multiplications and MAC (Multiply and Accumulation) operations causing most of core cycles of ARM926EJ-S, and also based on analysis of ARMv5 instructions. The result of optimization was evaluated on the basis of MIPS (Million Instruction per second). Implementation results show that BSAC bitstream at 96kbps can be decoded in real-time at 65MHz CPU clocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• The Journal of the Acoustical Society of Korea
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• v.25 no.4E
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• pp.137-141
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• 2006

This paper presents HE-AAC decoder optimization on TMS320C55x fixed-point DSP core using a DSP-C like FFR code, which provides fast and flexible porting to a DSP core. Our optimization efforts are focused on methodologies that include general optimization methods of FFR code suitable for general DSP or RISC platform in high-level language and software optimization methods in assembly language level. The implementation result requires 48 MIPS and 135 Kbytes memory space to decode 48 Kbps stereo using real Korean S-DMB data.