• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• ETRI Journal
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• v.38 no.1
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• pp.100-111
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• 2016

This paper presents a low-complexity channel-adaptive reconfigurable $4{\times}4$ QR-decomposition and M-algorithm-based maximum likelihood detection (QRM-MLD) multiple-input and multiple-output (MIMO) detector. Two novel design approaches for low-power QRM-MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM-MLD MIMO detector (where the M-value represents the number of survival branches in a stage) for dynamically adapting to time-varying channels is also proposed in this work. The proposed reconfigurable QRM-MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM-based QRM-MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of $4{\times}4$ MIMO with 64-QAM. Under time-varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.255-266
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• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.447-448
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• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.4738-4758
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• 2017

Resource allocation plays a crucial role in multiuser multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) systems to improve overall system performance. While previously proposed resource allocation algorithms are mainly designed from the point of view of the information-theoretic, we formulate the resource allocation problem as an average bit error rate (BER) minimization problem subject to a total power constraint when considering employing realistic MIMO detection techniques. Subsequently, we derive the optimal subcarrier and power allocation algorithms for three types of well-known MIMO detectors, including the maximum likelihood (ML) detector, linear detectors, and successive interference cancellation (SIC) detectors. To reduce the complexity, we also propose a two-step suboptimal algorithm that separates subcarrier and power allocation for each detector. We also analyze the diversity gain of the proposed suboptimal algorithms for various MIMO detectors. Simulation results confirm that the proposed suboptimal algorithm for each detector can achieve a comparable performance with the optimal allocation with a much lower complexity. Moreover, it is shown that the suboptimal algorithms perform better than the conventional algorithms that are known in the literature.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.220-226
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• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.17-26
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• 2004

This paper proposes JBSTBC (Joint Beamforming Space-Time Block Coding) scheme for MIMO (Multi-Input Multi-Output) communication systems. To enhance the order of spatial diversity in presence of deteriorative fading correlations as well as inter-substream interferences, the proposed JBSTBC method employs joint eigen-beamforming technique together with the BOLD (block-ordered layered detector) for MIMO-STBC. In order to confirm superiority of the proposed JBSTBC method, the computer simulations are conducted in highly correlated fading situations with providing detailed mathematical derivations for clarifying functionality of the proposed scheme.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1164-1171
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• 2006

In this paper, a simple and nonlinear MMSE detector is derived from the conventional linear MMSE detector to improve the system performance in turbo processing MIMO system and a new turbo processing MIMO system with nonlinear MMSE detector and Gaussian approximation is proposed. In turbo coded turbo processing MIMO system, the proposed system of M=N=4 performs about 0.5 dB better than the conventional system and the proposed system of M=N=8 performs about 0.4 dB better than conventional system at 1 % FER. In addition, the average number of outer iterations of proposed system shows lower than that of conventional system. This is caused by the fact that the nonlinear MMSE detector of proposed system decides soft-outputs of coded bits based on the observation of received signals, so that it can reduce the uncertainty region in estimating the coded bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.9
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• pp.528-534
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• 2014

In this paper, we propose an iterative detection and decoding scheme for the LDPC coded multiuser uplink massive-MIMO systems. We consider the simple maximal ratio combining (MRC) detector and LDPC decoder. We formulate the soft output of MRC detector and the relation between the extrinsic informations of the detector and decoder. The performance improvement of the proposed iterative detection and decoding scheme is shown by computer simulation.

• ETRI Journal
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• v.39 no.3
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.