• Journal of the Korean Society for Precision Engineering
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• v.22 no.10 s.175
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• pp.195-201
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• 2005

A laterally driven electromagnetic microactuator (LaDEM) is presented, and a micro-optical switch is designed and fabricated as a possible application. LaDEM provides parallel actuation of the microactuator to the silicon substrate surface (in-plane mode) by the Lorentz force. Poly-silicon-on-insulator (Poly-SOI) wafers and a reactive ion etching (RIE) process were used to fabricate high-aspect-ratio vertical microstructures, which allowed the equipment of a vertical micro mirror. A fabricated arch-shaped leaf spring has a thickness of $1.8{\mu}m$, width of $16{\mu}m$, and length of $800{\mu}m$. The resistance of the fabricated structure fer the optical switch was approximately 5$\Omega$. The deflection of the leaf springs increases linearly up to about 400 mA and then it demonstrates a buckling behavior around the current value. Owing to this nonlinear phenomenon, a large displacement of $60{\mu}m$ could be measured at 566 mA. The displacement-load relation and some dynamic characteristics are analyzed using the finite element simulations.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.939-946
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• 2018

In this work, we present simple schematics for a three-terminal graphene-based nanoelectromechanical switch with the vertical electrode, and we investigated their operational dynamics via classical molecular dynamics simulations. The main structure is both the vertical pin electrode grown in the center of the square hole and the graphene covering on the hole. The potential difference between the bottom gate of the hole and the graphene of the top cover is applied to deflect the graphene. By performing classical molecular dynamic simulations, we investigate the nanoelectromechanical properties of a three-terminal graphene-based nanoelectromechanical switch with vertical pin electrode, which can be switched by the externally applied force. The elastostatic energy of the deflected graphene is also very important factor to analyze the three-terminal graphene-based nanoelectromechanical switch. This simulation work explicitly demonstrated that such devices are applicable to nanoscale sensors and quantum computing, as well as ultra-fast-response switching devices.

• Korean Journal of Optics and Photonics
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• v.17 no.1
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• pp.7-17
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• 2006

In this paper, we proposed an optical true time-delay (TTD) for planar phased array antennas (PAAs), which is composed of a wavelength-dependent optical true time delay (WDOTTD) followed by a wavelength-independent optical true time delay (WIOTTD). The WDOTTD is a fiber Bragg gratings (FBGs) Prism and the WDOTTD is a fiber delay-lines matrix of which each component consists of a certain length of fiber connected to cross-ports of a 2${\times}$2 MEMS switch. A 10-GHz 2-bit${\times}$4-bit two-dimensional optical TTD has been fabricated by cascading a WDOTTD with a maximum time delay of 810 ps to a WIOTTD of $\pm$50 ps. Time delay and insertion loss for each radiation angle have been measured. Time delay error for the WIOTTD has been measured to be less than $\pm$1 ps. We have also designed a two-dimensional 10-GHz PAA composed of 8${\times}$8 microstrip patch antenna elements driven by the proposed TTD. The radiation patterns of this PAA have been obtained by simulation and analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.