• Journal of information and communication convergence engineering
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• 제12권4호
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• pp.252-256
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• 2014

Traditional block cipher Advanced Encryption Standard (AES) is widely used in the field of network security, but it has high overhead on each operation. In the 15th international workshop on information security applications, a novel lightweight and low-power encryption algorithm named low-power encryption algorithm (LEA) was released. This algorithm has certain useful features for hardware and software implementations, that is, simple addition, rotation, exclusive-or (ARX) operations, non-Substitute-BOX architecture, and 32-bit word size. In this study, we further improve the LEA encryptions for cloud computing. The Web-based implementations include JavaScript and assembly codes. Unlike normal implementation, JavaScript does not support unsigned integer and rotation operations; therefore, we present several techniques for resolving this issue. Furthermore, the proposed method yields a speed-optimized result and shows high performance enhancements. Each implementation is tested using various Web browsers, such as Google Chrome, Internet Explorer, and Mozilla Firefox, and on various devices including personal computers and mobile devices. These results extend the use of LEA encryption to any circumstance.

• Journal of Positioning, Navigation, and Timing
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• 제9권2호
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• pp.43-50
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• 2020

In this paper a low power Spreading Code Authentication (SCA) sequence with a BPSK(1) modulation at a frequency offset of +7.161 MHz is tested for authentication purposes, the Galileo E1OS is used as base signal. The tested signals comprise a Galileo constellation with 5 satellites including the Galileo OS Navigation Message Authentication (OSNMA) and a low power offset BPSK (OBPSK(7,1)) as SCA component. The signals are generated with the software based MuSNAT-Signal-Generator. The generated signals were transmitted Over-The-Air (OTA) using a Software-Defined-Radio (SDR) as pseudolite. With a real-environment-testbed the performance of the SCA in real channel conditions (fading and multipath) was tested. A new SCA evaluation scheme is proposed and was implemented. Under real channel conditions we derive experimental threshold values for the new SCA evaluation scheme which allow a robust authentication. A Security Code Estimation and Replay (SCER) spoofing attack was mimicked on the real-environment-testbed and analyzed with the SCA evaluation scheme. It was shown that the usage of an OBPSK is feasible as an authentication method and can be used in combination with the OSNMA to improve the authentication robustness against Security SCER attacks.

• Journal of Computing Science and Engineering
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• 제3권3호
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• 대한임베디드공학회논문지
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• 제17권6호
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.

• 한국소프트웨어감정평가학회 논문지
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• 제15권1호
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• pp.103-107
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• 2019

최근 저전력 고속 디지털 데이터 통신을 구현 하기위해 많은 기술들이 개발되고 있는 추세이며 듀티사이클 보정에 관련된 기술도 그중 하나이다. 본 논문에서는 전압제어 링 발전기용 저-면적 듀티사이클 보정 회로를 제안하였다. 듀티사이클 보정 회로는 전압제어 링 발진기의 180도 위상차이를 이용하여 듀티사이클을 보정하는 회로이며, 제안된 저-면적 듀티사이클 회로는 기존의 플립플롭을 TSPC(True Single Phase Clocking) 플립플롭으로 변경하여 회로를 구성하였고 이로 인하여 저-면적 고성능 회로를 구현하였다. 일반적인 플립플롭을 대신하여 TSPC플립플롭을 사용하여 기존 회로 대비 저-면적으로 회로 구현이 가능하며 고속 동작에 용이하여 저-전력용 고성능 회로에 활용될 것으로 기대된다.

• 한국정보기술학회 영문논문지
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• 제10권1호
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• pp.99-109
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• 2020

As environmental pollution has become severe due to the rapid increase in pollutant generation in the air, measurement, collection, and analysis of atmospheric environment information plays an important role. However, it is difficult to measure the high-resolution and real-time atmospheric environment of the cities and tourist spots with high population mobility only by measuring equipment of stationary measuring stations. Therefore, this paper proposes a portable atmospheric environment measurement system for real-time measurement and monitoring of atmospheric environment information. The proposed system is a portable client with a low-power wireless communication method. It is possible to reliably transmit and receive the measured data through a multi-threaded server to monitor the trend of pollutants in the air in real-time.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.2082-2084
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• 1998

This paper presents a microcontroller-based electronic neon ballasts which is highly suitable for a multi-use and low power consumption by performing economical hardwares and variable software algorithms. Result of this study has the following functions : brightness control, frequency variable output, automatic lightening control, low power characteristics.

• International journal of advanced smart convergence
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• 제10권3호
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• pp.1-9
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• 2021

In the Internet of Thing (IoT) framework, massive machine-type communications (MMTC) have required large spectral efficiency. For this, non-orthogonal multiple access (NOMA) has emerged as an efficient solution. Recently, a non-successive interference cancellation (SIC) NOMA scheme has been implemented without loss. This lossless NOMA without SIC is achieved via correlated superposition coding (SC), in contrast to conventional independent SC. However, conventional minimum high-correlated SC for only 2-user NOMA schemes was investigated in the lossless 2-user non-SIC NOMA implementation. Thus, this paper investigates a 3-user low-correlated SC scheme, especially for an inflated achievable sum rate, with a design of 3-user low-correlated SC. First, we design the 3-user low-correlated SC scheme by taking the minimum sum rate between 3-user SIC NOMA and 3-user non-SIC NOMA, both with correlated SC. Then, simulations demonstrate that the low correlation in the direction of the first user's power allocation inflates the sum rate in the same direction, compared to that of conventional minimum high-correlated SC NOMA, and such inflation due to low correlation is also observed similarly, in the direction of the second user's power allocation. Moreover, we also show that the two low correlations of the first and second users inflates doubly in the both directions of the first and second users' power allocations. As a result, the proposed 3-user low-correlated SC could be considered as a promising scheme, with the inflated sum rate in the future fifth-generation (5G) NOMA networks.

• ETRI Journal
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• 제32권4호
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.