• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.71-78
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• 2015

Since most education organizations such as Universities have a plenty of PCs, much electric power can be wasted if their power states are not managed properly. This paper introduces the RPM(Remote Power Management) software system implemented to reduce a waste of PC power in Universities. The System manager can monitor power state of all PCs in a University and turn off PCs or change power states of PCs to low power states. The RPM consists of three software modules. First, Power Controller, which is installed in each user PC, saves the power by changing low power state by utilizing low power algorithm proposed in this paper. Also it reports power state of its PC to Power Server on the state changed. Second, Power Server module gathers power state information of all PCs, stores them in a DB, and sends all or some parts of the information to Power Viewer whenever the manager asks. The manager can turn off or change a certain PC to low power state. We evaluated the performance of power saving for the RPM and the result showed achievement of 40% power saving.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.14 no.11
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• pp.931-938
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• 2002

Combustion dynamics of a dry low NOx gas turbine have been measured by utilizing a dynamic pressure measurement system. The software part of the measurement system, implemented with a commercial general-purpose DASYLab version 5.6 code, basically acquires combustion dynamics signals, performs the FFT analysis, and displays the results. The gas turbine often experiences momentary combustion instability, especially when its combustion mode changes. It is found that the measurement system developed in the study may outperform the other commercial dynamic pressure measurement system. The developed system currently serves to monitor the combustion dynamics of the gas turbine.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.72-83
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• 2002

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.201-202
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• 2006

In this paper, we achieved software and hardware implementation of SHA-1 hash function for sensor network. We implemented the software to be compatible with TinySec. In hardware design, we optimized operation logics for small area of hardware and minimized data transitions of register memory for low power design. Designed the software and hardware is verified on commercial sensor motes and our secure motes respectively.

• The KIPS Transactions:PartD
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• v.19D no.4
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• pp.281-292
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• 2012

A wide variety of smartphone applications is increasing the usage time of smartphone. Due to the increased time, it becomes difficult to providing stable services to users with limited battery capacity. The past works have been performed the power management of mobile device toward long-lasting battery development or low-power electric devices. However as the complexity of software embedded into system are increased, the research interests of the software power analysis is also increased. Among these studies on the software power analysis, model-based analysis technique is one of major interests because it can be able to analyze the power consumption before the development of source codes, then the analysis result can be used in the development of the software system, This paper suggests a model-based power analysis technique using UML state machine diagram. Our proposed technique estimates the power consumption by the simulation of Perti-net which is transformed from the state machine diagram.