• 센서학회지
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• 제27권1호
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• 한국컴퓨터정보학회논문지
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• 제19권4호
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• pp.25-33
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• 2014

본 논문에서는 멀티코어 프로세서 상에서 실시간 작업들의 데드라인들을 만족하면서 전력 소모량의 확률적 기대값을 최소화하는 문제를 해결하는 스케쥴링 기법을 제시하였다. 제시된 기법에서는 주어진 작업들의 불확실한 계산량을 과거의 계산량 분포에 기반하여 확률적 계산량으로 변환하고, 한정된 개수의 이산적 클락 주파수 값들을 이용하여 변환된 확률적 계산량의 전력 소모 기대 값을 최소화한다. 또한 시스템의 부하량이 적을 때에는 누수 전력을 고려하여 전체 코어들 중에서 일부의 코어들만을 사용하고 나머지 코어들의 전원을 소등시켜서 전력 소모량을 줄인다. 성능평가 실험에서 제시된 기법이 기존 방법의 전력 소모량을 최대 69%까지 감소시킴을 확인하였다.

• ETRI Journal
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• 제30권1호
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• ETRI Journal
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• 제37권1호
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• Journal of Biosystems Engineering
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• 제34권4호
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• pp.243-253
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• 2009

This research expands investigations into the biomass resource potential associated with California's food processing industry by surveying industries within a two county region in the San Joaquin Valley, California, USA. A previous survey conducted in 2005 for the Sacramento Municipal Utility District (SMUD) quantified residue and waste generation from food processors and food preparation businesses in the Sacramento region. The present survey investigates residue and waste streams from food processors located in Merced and Stanislaus Counties. Sixty food processors were identified to participate in the survey, of which 49 responded (82%) and data were acquired for 38 (63%) (6 facilities closed or moved, 8 decided not to participate). Within the two counties, total annual waste among survey respondents amounted to 24,044 dry tons of high moisture (${\geq}$60%) food residuals, 5,358 dry tons of low moisture (<60%) food residuals; and 23.7 million $m^3$ of wastewater containing 38,814 tons of biochemical oxygen demand ($BOD_5$). The total potential electric power generation from these food residues was estimated at approximately $7\;MW_e$. Total solid waste resource included in the survey response was estimated at about 10% of statewide residue generation for processors falling within the Standard Industrial Classification (SIC) System Major Group 20 (Food and Kindred Products) categories.

• ETRI Journal
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• 제35권4호
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• 한국컴퓨터정보학회논문지
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• 제14권12호
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• pp.9-16
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• 2009

최신의 멀티코어 프로세서를 설계할 때에는 성능과 함께 전력 효율성이 반드시 고려되어야 한다. 본 논문에서는 싱글 코어 프로세서의 명령어 캐쉬에서 소비되는 전력을 줄이기 위해 사용되는 대표적 기법중 하나인 필터 캐쉬 구조를 멀티 코어 프로세서에 적용하기 위한 새로운 방안을 제시하고자 한다. 명령어 캐쉬는 프로세서 전체에서 소비되는 전력의 상당 부분을 차지하고 있기 때문에, 변형 필터 캐쉬 구조를 이용한 저전력 명령어 캐쉬 설계는 멀티 코어 프로세서의 전력 소비를 줄이는데 있어서 중요한 역할을 담당할 수 있다. 제안하는 변형 필터 캐쉬 구조는 멀티코어 프로세서에서 필터 캐쉬에 대한 희생 캐쉬를 추가함으로써 1차 명령어 캐쉬에 대한 접근 횟수를 감소시키는 방법을 이용하여 명령어 캐쉬에서 소비되는 총전력을 줄일 수 있다. 제안하는 명령어 캐쉬 구조의 효율성을 분석하기 위한 모의 실험 도구로 SimpleScalar시뮬레이터와 CACTI를 사용한다. 모의실험 결과, 제안하는 기술은 멀티코어 프로세서의 명령어 캐쉬에서 소비되는 전력을 기존의 필터 캐쉬 구조와 비교하여 최대 3.4% 감소시킬 수 있음을 확인할 수 있다. 더욱이 제안하는 구조는 기존의 필터 캐쉬 구조에 비해 보다 우수한 성능을 보여준다.

• 디지털콘텐츠학회 논문지
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• 제15권3호
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• pp.433-438
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• 2014

본 논문은 배터리와 태스크를 고려한 저전력 알고리듬을 제안하였다. 제안한 알고리듬은 배터리의 용량과 사용 목표 시간에 따른 단위 시간의 소모 전력을 설정한다. 주어진 모든 태스크들의 소모 전력을 계산한다. 태스크들 중에서 소모 전력이 가장 큰 태스크의 소모 전력과 소모 전력이 가장 작은 태스크의 소모 전력의 평균을 구한다. 태스크의 소모 전력의 평균을 단위 시간을 고려하여 다시 소모 전력을 계산한다. 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 작거나 같을 경우 태스크의 평균 소모 전력보다 큰 태스크 들을 대상으로 저전력을 수행한다. 또한, 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 클 경우 계산된 소모 전력의 평균보다 큰 태스크 들을 대상으로 저전력을 수행한다. 저전력은 태스크의 프로세서와 디바이스의 소모 전력을 분할하여 소모 전력이 큰 부분에 대해 저전력을 수행한다. 실험은 배터리를 고려한 저전력 알고리듬인 [6]과 비교하였다. 실험결과 [6]보다 소모 전력이 감소되어 알고리듬의 효율성이 입증되었다.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2014년도 제49차 동계학술대회논문집 22권1호
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.