• Journal of the Korea Institute of Military Science and Technology
• /
• v.15 no.6
• /
• pp.812-819
• /
• 2012

Interference and jamming are becoming increasing concern to a radar system nowdays. AESA(Active Electronically Steered Array) antennas and adaptive beamforming(ABF), in which antenna beam patterns can be modified to reject the interference, offer a potential solution to overcome the problems encountered. In this paper, we've developed a planar active phased array radar system, in which ABF, target detection and tracking algorithm operate in real-time. For the high output power and the low noise figure of the antenna, we've designed the S-band TRMs based on GaN HEMT. For real-time processing, we've used wavelenth division multiplexing technique on fiber optic communication which enables rapid data communication between the antenna and the signal processor. Also, we've implemented the HW and SW architecture of Real-time Signal Processor(RSP) for adaptive beamforming that uses SMI(Sample Matrix Inversion) technique based on MVDR(Minimum Variance Distortionless Response). The performance of this radar system has been verified by near-field and far-field tests.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.7
• /
• pp.1608-1616
• /
• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.05a
• /
• pp.435-438
• /
• 2003

The MS card data transfer system using blue-tooth protocol ran communicate the MS card data wirelessly and does not take an extra communication expense which is a weakness point of existing wireless communication system. This Blue-tooth system, which has excellent security and no extra communication expense, can efficiently communicate data of the place ,where can be solved with small scale wireless network, such as the theme-park or gasoline-station. Existing wireless communication system compose network using wireless-LAN protocol which has extra communication expense, or with RF protocol which has poor security. But this system suitable for LAN because it has not extra communication expense and it has excellent security cause frequency-hopping of Blue-tooth protocol. The MS card data transfer system using blue-tooth protocol has low power, high performance RISC processor and large scale 16-gray graphic LCD which is suitable for portable unit. The MS card data transfer system can efficiently control depot for a long time because it has low power, excellent security and no extra communication expense.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.8 no.2
• /
• pp.151-164
• /
• 2003

In this paper, induction motor drives with low switching acoustic noise based on the 2 phase modulated RLL(Random Lead-Lag) PWM is proposed and implemented. The proposed switching method is much bettor than 3 phase modulated RLL-PWM from the standpoint of the broadening effect of the acoustic noise spectrum. Along with the randomization of PWM Pulses, SVM(Space Vector Modulation) is executed in the TMS320C31 DSP(Digital Signal Processor). To verify the validity of the proposed RPWM(Random PWM), the experimental study was tried. The experimental results show that the performance of the proposed method and the 3 phase center-aligned SVM / conventional RLL-PWM are nearly the same from the viewpoint of the constant v/f centrel. But, in case of the proposed 2 phase modulated RLL-PWM, the spectrum characteristics of the voltage and the switching acoustic noise are shown to have better broadening effect than 3 phase modulated one.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.2
• /
• pp.202-208
• /
• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.631-634
• /
• 2009

Recent advances in wireless communication, electronics, MEMS device, sensor and battery technology have made it possible to manufacture low-cost, low-power, multi-function tiny sensor nodes. A large number of tiny sensor nodes form sensor network through wireless communication. Sensor networks represent a significant improvement over traditional sensors, research on Zigbee wireless image transmission has been a topic in industrial and scientific fields. In this paper, we design a Zigbee wireless image sensor node and multimedia monitoring server system. It consists of embedded processor, memory, CMOS image sensor, image acquisition and processing unit, Zigbee RF module, power supply unit and remote monitoring server system. In the future, we will further improve our Zigbee wireless image sensor node and monitoring server system. Besides, energy-efficient Zigbee wireless image transmission protocol and interworking with mobile network will be our work focus.

• Smart Structures and Systems
• /
• v.6 no.5_6
• /
• pp.731-748
• /
• 2010

Impact detection and health monitoring are very important tasks for civil infrastructures, such as bridges. Piezoceramic based transducers are widely researched for these tasks due to the piezoceramic material's inherent advantages of dual sensing and actuation ability, which enables the active sensing method for structural health monitoring with a network of piezoceramic transducers. Wireless sensor networks, which are easy for deployment, have great potential in health monitoring systems for large civil infrastructures to identify early-age damages. However, most commercial wireless sensor networks are general purpose and may not be optimized for a network of piezoceramic based transducers. Wireless networks of piezoceramic transducers for active sensing have special requirements, such as relatively high sampling rate (at a few-thousand Hz), incorporation of an amplifier for the piezoceramic element for actuation, and low energy consumption for actuation. In this paper, a wireless network is specially designed for piezoceramic transducers to implement impact detection and active sensing for structural health monitoring. A power efficient embedded system is designed to form the wireless sensor network that is capable of high sampling rate. A 32 bit RISC wireless microcontroller is chosen as the main processor. Detailed design of the hardware system and software system of the wireless sensor network is presented in this paper. To verify the functionality of the wireless sensor network, it is deployed on a two-story concrete frame with embedded piezoceramic transducers, and the active sensing property of piezoceramic material is used to detect the damage in the structure. Experimental results show that the wireless sensor network can effectively implement active sensing and impact detection with high sampling rate while maintaining low power consumption by performing offline data processing and minimizing wireless communication.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.7
• /
• pp.977-985
• /
• 2021

The LiDAR sensor is attracting attention as a key sensor for autonomous driving vehicle. LiDAR sensor provides measured three-dimensional lengths within range using LASER. However, as much data is provided to the external system, it is difficult to process such data in an external system or processor of the vehicle. To resolve these issues, we develop integrated processing system for LiDAR sensor. The system is configured that client receives data from LiDAR sensor and processes data, server gathers data from clients and transmits integrated data in real-time. The test was carried out to ensure real-time processing of the system by changing the data acquisition, processing method and process driving method of process. As a result of the experiment, when receiving data from four LiDAR sensors, client and server process was operated using background or multi-core processing, the system response time of each client was about 13.2 ms and the server was about 12.6 ms.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.11_12
• /
• pp.663-674
• /
• 2005

We propose a system aimed at achieving high energy-delay efficiency by using adaptive victim caches. Particularly, we investigate methods to improve the hit rates in the first level of memory hierarchy, which reduces the number of accesses to mort power consuming memory structures such as L2 cache. Victim cache is a memory element for reducing conflict misses in a direct-mapped L1 cache. We present two techniques to fill the victim cache with the blocks that have higher probability to be re-reqeusted by processor. Hit-based victim cache ks tilled with the blocks which were referenced frequently by processor. Replacement-based victim cache is filled with the blocks which were evicted from the sets where block replacements had happened frequently According to our simulations, replacement-based victim cache scheme outperforms the conventional victim cache scheme about $2\%$ on average and refutes the power consumption by up to $8\%$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.15-23
• /
• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.