• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제11권1호
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• pp.67-73
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• 2011

With the rapid growth of recent smart phone technology, the interests for the design of online game in mobile computing environment are highly focussed on with great attention. Smart phone as a mobile terminal device, however, has many restrictions for implementing online mobile game since the limitation of relatively low performance of a processor, low resolution of GUI, small memory spaces, and short battery power. Therefore, most of games are very restricted on online and multi-play functions. In this paper, we design and implement mobile online game app in component based smart phone environment in order to take over these restrictions in mobile environment. Especially, the implemented mobile game is able to play online game among Wi-Fi based game server and another smart phone.

• Proceedings of the KOSOMBE Conference
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• 대한의용생체공학회 1996년도 추계학술대회
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• pp.22-24
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• 1996

Small size DC motor control method for portable drug delivery system has been developed to be used for the actuator of insulins pump. The control method gives the controllabilities both in high speed(40-50 revolution per second(rps)) DC motor drive and also in low speed(0.5-1rps). In low speed mode DC motor is controlled to act like stepping motor and in high speed to optimize power consumption. To control both mode modified bang bang control is suggested. Using this method small size DC motor(spec.) speed is controlled from 0.2 rps to 50 rps. Experimental setup is developed using micro-processor(PIC16C73, Micro Chips co., USA), motor turns checking circuitry, small size DC motor for pager(SM1012, Samhong co., Korea) and gear box. Results from experiment meet need for vailable load condition which is require for portable drug delivery system.

• Korean Journal of Artificial Intelligence
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• 제9권2호
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• pp.23-28
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• 2021

In this paper, we studied a system that can efficiently build security management for single-person households using Arduino, ESP32-CAM and PIR sensors, and proposed an Android app with an internet connection. The ESP32-CAM is an Arduino compatible board that supports both Wi-Fi, Bluetooth, and cameras using an ESP32-based processor. The PCB on-board antenna may be used independently, and the sensitivity may be expanded by separately connecting the external antenna. This system has implemented an Arduino-based Unauthorized intrusion system that can significantly help prevent crimes in single-person households using the combination of PIR sensors, Arduino devices, and smartphones. unauthorized intrusion system, showing the connection between Arduino Uno and ESP32-CAM and with smartphone applications. Recently, if daily quarantine is underway around us and it is necessary to verify the identity of visitors, it is expected that it will help maintain a safety net if this system is applied for the purpose of facial recognition and restricting some access. This technology is widely used to verify that the characters in the two images entered into the system are the same or to determine who the characters in the images are most similar to among those previously stored in the internal database. There is an advantage that it may be implemented in a low-power, low-cost environment through image recognition, comparison, feature point extraction, and comparison.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권12호
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제45권5호
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제36C권12호
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제6권3호
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제21권5호
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제22권9호
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• pp.1257-1263
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• 2018

Secure authentication technology is a fundamental building block for secure services for Internet of Things devices. Particularly, the multiplication operation is a core operation of public key cryptography, such as RSA, ECC, and SIDH. However, modern low-power processor, namely ARM Cortex-M3 processor, is not secure enough for practical usages, since it executes the multiplication operation in variable-time depending on the input length. When the execution is performed in variable-time, the attacker can extract the password from the measured timing. In order to resolve this issue, recent work presented constant-time solution for multiplication operation. However, the implementation still missed various speed-optimization techniques. In this paper, we analyze previous multiplication methods over ARM Cortex-M3 and provide optimized implementations to accelerate the speed-performance further. The proposed method successfully accelerates the execution-time by up-to 25.7% than previous works.

• Journal of the Korea Society of Computer and Information
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• 제13권6호
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• pp.33-39
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• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.