• 제목/요약/키워드: Low-power encryption

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Low-Power Encryption Algorithm Block Cipher in JavaScript

  • Seo, Hwajeong;Kim, Howon
    • Journal of information and communication convergence engineering
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    • 제12권4호
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    • pp.252-256
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    • 2014
  • Traditional block cipher Advanced Encryption Standard (AES) is widely used in the field of network security, but it has high overhead on each operation. In the 15th international workshop on information security applications, a novel lightweight and low-power encryption algorithm named low-power encryption algorithm (LEA) was released. This algorithm has certain useful features for hardware and software implementations, that is, simple addition, rotation, exclusive-or (ARX) operations, non-Substitute-BOX architecture, and 32-bit word size. In this study, we further improve the LEA encryptions for cloud computing. The Web-based implementations include JavaScript and assembly codes. Unlike normal implementation, JavaScript does not support unsigned integer and rotation operations; therefore, we present several techniques for resolving this issue. Furthermore, the proposed method yields a speed-optimized result and shows high performance enhancements. Each implementation is tested using various Web browsers, such as Google Chrome, Internet Explorer, and Mozilla Firefox, and on various devices including personal computers and mobile devices. These results extend the use of LEA encryption to any circumstance.

Enabling Energy Efficient Image Encryption using Approximate Memoization

  • Hong, Seongmin;Im, Jaehyung;Islam, SM Mazharul;You, Jaehee;Park, Yongjun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권3호
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    • pp.465-472
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    • 2017
  • Security has become one of the most important requirements for various devices for multi-sensor based embedded systems. The AES (Advanced Encryption Standard) algorithm is widely used for security, however, it requires high computing power. In order to reduce the CPU power for the data encryption of images, we propose a new image encryption module using hardware memoization, which can reuse previously generated data. However, as image pixel data are slightly different each other, the reuse rate of the simple memoization system is low. Therefore, we further apply an approximate concept to the memoization system to have a higher reuse rate by sacrificing quality. With the novel technique, the throughput can be highly improved by 23.98% with 14.88% energy savings with image quality loss minimization.

고속 모뎀에서의 AES-CCM 보안 모드 구현에 관한 연구 (Research on the Implementation of the AES-CCM Security Mode in a High Data-Rate Modem)

  • 이현석;박승권
    • 전기학회논문지P
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    • 제60권4호
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    • pp.262-266
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    • 2011
  • In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

AES 기반 화이트박스 암호 기법의 지연 시간과 연산량 분석 (Analysis of Latency and Computation Cost for AES-based Whitebox Cryptography Technique)

  • 이진민;김소연;이일구
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2022년도 춘계학술대회
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    • pp.115-117
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    • 2022
  • 화이트박스 암호 기법은 암호 키 정보를 소프트웨어 기반 암호화 알고리즘에 섞어 암호 키의 노출을 막는 방식이다. 화이트박스 암호 기법은 허가되지 않은 역공학 분석으로 메모리에 접근하여 기밀 데이터와 키를 유추하기 어렵게 만들어서 종래의 하드웨어 기반의 보안 암호화 기법을 대체하는 기술로 주목받고 있다. 하지만, 암복호화 과정에서 연산 결과와 암호 키를 숨기기 위해 크기가 큰 룩업테이블을 사용하기 때문에 암복호 속도가 느리고, 메모리 사이즈가 커지는 문제가 발생한다. 특히 최근 저가, 저전력, 경량의 사물인터넷 제품들은 제한된 메모리 공간과 배터리 용량 때문에 화이트박스 암호을 적용하기 어렵다. 또한, 실시간 서비스를 지원해야 하는 네트워크 환경에서는 화이트박스 암호의 암복호화 속도로 인해 응답 지연 시간이 증가하여 통신 효율이 열화된다. 따라서 본 논문에서는 S.Chow가 제안한 AES 기반 화이트박스(WBC-AES)를 사용하여 속도와 메모리 요구조건을 만족할 수 있는지 실험 결과를 토대로 분석한다.

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Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

  • Song, Oh-Young;Kim, Ji-Ho
    • Journal of Electrical Engineering and Technology
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    • 제6권3호
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    • pp.418-422
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    • 2011
  • For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

IoT/QR/전자태그용 저용량 메시지 데이터 암호화 적용을 위한 새로운 방식의 스트림 경량 암호화 알고리즘 모티브 제안 (A new type of lightweight stream encryption algorithm motif for applying low capacity messaging data encryption for IoT / QR / electronic tags)

  • 김정훈
    • 한국정보전자통신기술학회논문지
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    • 제10권1호
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    • pp.46-56
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    • 2017
  • 최근 IoT 기술의 확산이 본격화 되면서, 홈/가전/의료등 전 산업 분야에 적용되고 있는데, IoT의 저 사양, 저 전력 소모 특성과 통신 데이터 특성으로 인하여, 기존 암호화 알고리즘의 적용이 용이하지 않으며, 따라서 보안 위협에 대한 우려가 커지고 있다. 이에 대응하여 본 연구에서는, 기존의 고정비트에 대한 XOR연산을 이용한 스트림 암호화 방식에 비하여, 해당 기준 비트에서 상위 방향의 비트 패턴에 따라 불규칙적으로 결정되는 특정한 바이너리 클러스터를 기준으로 암호 키 값에 따라 자리내림, 자리올림 방식을 이용하여, 비트 값에 변화를 주는 일종의 가변 길이 비트 XOR연산 방식을 도입하여 암호화 및 복호화가 진행될 수 있음을 처음으로 제시하였다. 제안 알고리즘의 특징상 암호화 전후의 데이터 크기 변화가 없고, IoT 디바이스/QR코드/RFID/NFC가 빈번히 처리하는 짧은 메시지 데이터에 대해서도 암호화하는 실용성을 확인하였다.

A Hierarchical Bilateral-Diffusion Architecture for Color Image Encryption

  • Wu, Menglong;Li, Yan;Liu, Wenkai
    • Journal of Information Processing Systems
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    • 제18권1호
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    • pp.59-74
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    • 2022
  • During the last decade, the security of digital images has received considerable attention in various multimedia transmission schemes. However, many current cryptosystems tend to adopt a single-layer permutation or diffusion algorithm, resulting in inadequate security. A hierarchical bilateral diffusion architecture for color image encryption is proposed in response to this issue, based on a hyperchaotic system and DNA sequence operation. Primarily, two hyperchaotic systems are adopted and combined with cipher matrixes generation algorithm to overcome exhaustive attacks. Further, the proposed architecture involves designing pixelpermutation, pixel-diffusion, and DNA (deoxyribonucleic acid) based block-diffusion algorithm, considering system security and transmission efficiency. The pixel-permutation aims to reduce the correlation of adjacent pixels and provide excellent initial conditions for subsequent diffusion procedures, while the diffusion architecture confuses the image matrix in a bilateral direction with ultra-low power consumption. The proposed system achieves preferable number of pixel change rate (NPCR) and unified average changing intensity (UACI) of 99.61% and 33.46%, and a lower encryption time of 3.30 seconds, which performs better than some current image encryption algorithms. The simulated results and security analysis demonstrate that the proposed mechanism can resist various potential attacks with comparatively low computational time consumption.

Low area field-programmable gate array implementation of PRESENT image encryption with key rotation and substitution

  • Parikibandla, Srikanth;Alluri, Sreenivas
    • ETRI Journal
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    • 제43권6호
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    • pp.1113-1129
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    • 2021
  • Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

Towards Choosing Authentication and Encryption: Communication Security in Sensor Networks

  • Youn, Seongwook;Cho, Hyun-chong
    • Journal of Electrical Engineering and Technology
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    • 제12권3호
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    • pp.1307-1313
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    • 2017
  • Sensor networks are composed of provide low powered, inexpensive distributed devices which can be deployed over enormous physical spaces. Coordination between sensor devices is required to achieve a common communication. In low cost, low power and short-range wireless environment, sensor networks cope with significant resource constraints. Security is one of main issues in wireless sensor networks because of potential adversaries. Several security protocols and models have been implemented for communication on computing devices but deployment these models and protocols into the sensor networks is not easy because of the resource constraints mentioned. Memory intensive encryption algorithms as well as high volume of packet transmission cannot be applied to sensor devices due to its low computational speed and memory. Deployment of sensor networks without security mechanism makes sensor nodes vulnerable to potential attacks. Therefore, attackers compromise the network to accept malicious sensor nodes as legitimate nodes. This paper provides the different security models as a metric, which can then be used to make pertinent security decisions for securing wireless sensor network communication.

저 사양 IoT 장치간의 암호화 알고리즘 성능 비교 (Comparison of encryption algorithm performance between low-spec IoT devices)

  • 박정규;김재호
    • 사물인터넷융복합논문지
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    • 제8권1호
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    • pp.79-85
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    • 2022
  • 사물인터넷(IoT)은 다양한 플랫폼, 컴퓨팅 성능, 기능을 가지는 장치를 연결한다. 네트워크의 다양성과 IoT 장치의 편재로 인해 보안 및 개인 정보 보호에 대한 요구가 증가하고 있다. 따라서 암호화 메커니즘은 이러한 증가된 요구 사항을 충족할 만큼 충분히 강력해야 하고 동시에 저 사양의 장치에 구현될 수 있을 만큼 충분히 효과적이어야 한다. 논문에서는 IoT에서 사용할 수 있는 다양한 유형의 장치에 대한 최신 암호화 기본 요소 및 체계의 성능 및 메모리 제한 사항을 제시한다. 또한, IoT 네트워크에 자주 사용되는 저 사양의 장치에서 가장 일반적으로 사용되는 암호화 알고리즘의 성능에 대한 자세한 성능 평가를 수행한다. 데이터 보호 기능을 제공하기 위해 바이너리 링에서 암호화 비대칭 완전 동형 암호화와 대칭 암호화 AES 128비트를 사용했다. 실험 결과 IoT 장치는 대칭 암호를 구현하는데 충분한 성능을 가지고 있었으나 비대칭 암호 구현에서는 성능이 저하되는 것을 알 수 있다.