• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.5
• /
• pp.315-321
• /
• 2009

Remote water meter monitoring is essential in U-city applications, whoγe digital water meter is a key component. While there are several kinds of water meters, the way to use has sensors has the merit of better preciseness, but the drawback of more power consumption. In this paper, we suggest an advanced sensing algorithm to diminish the power consumption while keeping the quality of preciseness. Our approach is to use less precise hall sensor for detecting the start of water impeller rotation with lower power consumption. During the rotation, a high precision hall sensor is used to meter the amount of water consumption. Our algorithm is analyzed to get 2 times lower power consumption than the previous algorithm.

• Journal of information and communication convergence engineering
• /
• v.16 no.2
• /
• pp.130-134
• /
• 2018

Wireless capsule endoscopy (WCE) is considered as recent technology for the detection cancer cells in the human digestive system. WCE sends the captured information from inside the body to a sensor on the skin surface through a wireless medium. In WCE, the design of low-power consumption devices is a challenging topic. In the Shannon-Nyquist sampling theorem, the number of samples should be at least twice the highest transmission frequency to reconstruct precise signals. The number of samples is proportional to the power consumption in wireless communication. This paper proposes compressive sensing as a method to reduce power consumption in WCE, by means of a trade-off between samples and reconstruction accuracy. The proposed scheme is validated under channel constraints, expressed as the realistic human body path loss. The results show that the proposed scheme achieves a significant reduction in WCE power consumption and achieves a faster computation time with low signal error reconstruction.

• International Journal of Contents
• /
• v.7 no.1
• /
• pp.1-7
• /
• 2011

A new power control algorithm for wireless communication which can be applied to various near distance communications and USN/RFID systems is proposed. This technique has been applied and tested to lithium coin battery operated UHF/microwave transceiver systems to show extremely long communication life time without battery exchange. The power control algorithm is based on the dynamic prediction method of arrival time for incoming packet at the receiver. We obtain 16mA current consumption in the TX module and 20mA current consumption in the RX module. The advantage provided by this method compared to others is that both master transceiver and slave transceiver can be low power consumption system.

• ETRI Journal
• /
• v.25 no.5
• /
• pp.288-296
• /
• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.4
• /
• pp.462-466
• /
• 2010

A new buffer cache management scheme that aims at reducing power consumption in mixed HDD and NAND flash memory storage systems is presented. The proposed scheme reduces power consumption by considering different energy-consumption rate of storage devices, I/O operation type (read or write), and reference potential of cached blocks in terms of both recency and frequency. Simulation shows that the proposed scheme reduces power consumption by 18.0% on average and up to 58.9%.

• Journal of information and communication convergence engineering
• /
• v.5 no.1
• /
• pp.59-63
• /
• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of Korea Multimedia Society
• /
• v.19 no.7
• /
• pp.1179-1187
• /
• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.144-147
• /
• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.563-569
• /
• 2015

For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEM-relay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.3
• /
• pp.586-594
• /
• 2014

Maximizing the operating time by reducing the power consumption is important factor to operate sensor network under water networks. For efficient power consumption, dynamic voltage scaling method is available. This method operates low frequency when there is no workload. In case of abundant workload, high frequency operation completes hard work within short time, reducing power consumption. For this reason, complex cryptography should be computed in high frequency. In this paper, we apply dynamic voltage scaling method to cryptography and show performance evaluation. With this result, we can reduce power consumption for cryptography in under water communication.