• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.401-407
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• 2010

In this paper, we consider a low-complex companding technique for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) systems. For the technique, we propose a novel companding function to compensate the problem of the conventional companding functions which are difficult to design complying with system requirements and deteriorate the bit error rate (BER) performance significantly. The proposed scalable companding function can provide an arbitrary value of the maximum PAPR with which the BER performance changes gracefully. In addition, the proposed companding function can be designed readily according to the PAPR and BER performance required by the system and is observed to provide better BER performance than the conventional clipping and $\mu$-low companding schemes under the similar PAPR condition.

• Journal of the Optical Society of Korea
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• v.6 no.3
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• pp.105-107
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• 2002

We propose 'variable decision threshold technique' to decrease the power penalty induced by low-frequency tones. The proposed scheme uses a simple low-speed receiver to change the decision threshold of the optical receiver according to the low-frequency tones. We demonstrate the proposed method at 2.5 Gb/s.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.8
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• pp.3918-3934
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• 2017

This paper presents a viewport resolution scaling technique to reduce power consumption in mobile graphic processing units (GPUs). This technique controls the rendering resolution of applications in proportion to the resolution factor. In the mobile environment, it is essential to find an effective resolution factor to achieve low power consumption because both the resolution and power consumption of a GPU are in mutual trade-off. This paper presents a resolution factor that can minimize image quality degradation and gain power reduction. For this purpose, software and hardware viewport resolution scaling techniques are applied in the Android environment. Then, the correlation between image quality and power consumption is analyzed according to the resolution factor by conducting a benchmark analysis in the real commercial environment. Experimental results show that the power consumption decreased by 36.96% on average by the hardware viewport resolution scaling technique.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.27-33
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• 2011

In this paper, we propose a high gain, current reused ultra wideband (UWB) low noise amplifier (LNA) that uses TSMC 0.18 ${\mu}m$ CMOS technology. To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized in the first stage. A ${\pi}$-type LC network is adopted in the second stage to achieve sufficient gain over the entire frequency band. The proposed UWB LNA has a voltage gain of 12.9~18.1 dB and a noise figure (NF) of 4.05~6.21 dB over the frequency band of interest (1~10 GHz). The total power consumption of the proposed UWB LNA is 10.1 mW from a 1.4 V supply voltage, and the chip area is $0.95{\times}0.9$ mm.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.2
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• pp.74-79
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• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1721-1724
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• 2017

This paper presents a numerical optimization technique to reduce input current and torque ripple of the low voltage BLDC motor using core, coil and switching angle optimization. The optimization technique is employed using the generalized response surface method(RSM) and sampling minimization technique with FEM. A 50W 24V BLDC motor is used to verify the proposed algorithm. As optimizing results, the input current is reduced from 2.46 to 2.11[A], and the input power is reduced from 59 [W] to 51 [W] at the speed of 1000 [rpm]. Also, applied the same optimization algorithm, the torque ripple is reduced about 7.4 %. It is confirmed that the proposed technique is a reasonably useful tool to reduce the consuming current and torque ripple of the low voltage BLDC motor for a compact and efficient design.

• Journal of Families and Better Life
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• v.27 no.4
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• pp.141-160
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• 2009

Recently, some policies for reducing standby power, which has quite an effect on electricity consumption, have been employed all over the world. This study surveys the present condition of standby power for major electric home appliances during three years and analyzes the result of technical development reducing standby power. It presents how the industry paid attention to applying the technique of reducing standby power to electric appliances and how it affects the product's energy efficiency. We survey the standby power's change for six items, which were selected from the major electric appliances available on the market. It analyzes the difference of standby power consumption between appliances with a standby power reducing technique and those without during the latest three years. The amount of the average standby power is also compared. The comparison data confirms that the industry's effort and application of reducing standby power contribution has contributed to increasing an appliance's energy efficiency. This study restricted the analyzed items to six appliances, which has been a low volunteered involvement in the standby power reducing program. It is important for reducing standby power consumption of appliances because it contributes to saving electric energy at home and abroad. The development of the standby power reducing technique is needed for more appliances. Along with the development of the standby power reducing technique in the industrial field, it also necessary for consumers to enlarge their understanding of standby power reduction for economic, social, and environmental values.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.337-340
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• 2002

This paper describes a phase compensation technique for the low power consumption OTA. Power consumption of the low power OTA is lower than that of the conventional Wang's OTA. However. this circuit has an oscillation problem. The phase margin is -24deg. By using the phase compensation capacitor, the phase margin becomes 52deg. As a result, the low power consumption OTA circuit becomes to have an enough phase margin and to operate stably.