• 대한전기학회논문지:시스템및제어부문D
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• 제55권12호
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• Current Optics and Photonics
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• 제2권5호
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• pp.431-435
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• 2018

A modified setup of a CMD technique for high power coherent beam combining was presented to address an issue of low damage threshold of electro-optic modulators. The feasibility of the modified setup was demonstrated by combining eight fiber beams, and it was successfully performed with ${\lambda}/44$ of residual phase error and 100 Hz of control bandwidth. It is expected that the modified CMD setup facilitates ultra-high power coherent beam combination without a limitation caused by the low damage threshold of electro-optic modulators.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.477-480
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• 2015

본 논문에서는 MPPT(Maximum Power Point Tracking) 제어 기능을 갖는 저전압 진동에너지 하베스팅 회로를 제안한다. 제안된 회로는 Bulk-driven technique을 적용하여 0.8V의 낮은 전압에서도 동작 가능하다. 압전소자의 출력단에 연결된 전파정류기의 개방회로 전압을 MPPT 제어회로를 통해 주기적으로 샘플링하고, 최대 가용전력 점의 전압을 부하에 전달한다. 제안된 회로는 0.35um CMOS 공정으로 설계되었으며, 패드를 포함한 칩 면적은 $1.33mm{\times}1.31mm$이다. 모의실험결과 설계된 회로의 최대 전력효율은 85.49%이다.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• ETRI Journal
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• 제25권5호
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• ETRI Journal
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• 제34권5호
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.892-895
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• 2011

SoC(System-On-Chip)을 테스트 하는 동안 소모하는 전력소모는 SoC내의 IP 코어가 증가됨에 따라 매우 중요한 요소가 되었다. 본 논문에서는 Scan Latch Reordering과 Clock Gating 기법을 적용하여 scan-in 전력소모를 줄이는 알고리즘을 제안한다. Scan vector들의 해밍거리를 최소로 하는 새로운 Scan Latch Reordering을 적용하였으며 Gated scan 셀을 사용하여 저전력을 구현하였다. ISCAS 89 벤치마크 회로에 적용하여 실험한 결과 모든 회로에 대하여 향상된 전력소모를 보였다.

• 열처리공학회지
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• 제5권2호
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• pp.122-132
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• 1992

This study has been performed to investigate into some effects of the power density and traverse speed of laser beam on the optical microstructure, hardness and wear characteristics of medium carbon low alloy steel treated by laser surface hardening technique. The results obtained from the experiment are summarized as follows : (1) Optical micrograph has shown that finer lath martensite is formed and the amount of undissolved complex carbides increases as the traverse speed increases under the condition of a given power density, whereas the coarsening of lath martensite and the reduction of undissolved complex carbides occur with increasing the power density at a given traverse speed. (2) Hardness measurements have revealed that as the traverse speed increases, hardness values of outermost surface layer more of less decrease under low power densities, but are uniformly distributed under high power densities, also showing that they are uniformly distributed at low traverse speeds and more or less decrease at high traverse speeds with increasing the power density. (3) The effective case depth has been found to decrease from 0.26 mm to 0.17 mm with increasing the traverse speed from 1.5 m/min to 3.0 m/min at a given power density of $25.48{\times}10^3w/cm^2$ and to increase from 0.20 mm to 0.36 mm with increasing the power density from $19.11{\times}10^3w/cm^2$ to $38.22{\times}10^3w/cm^2$ at a given traverse speed of 2.0 m/min. (4) Wear test has exhibited that the amount of weight loss of laser surface hardened specimen with respect to sliding distance at a given load increases with increasing traverse speed at a given power density and decreses with increasing power density at a given traverse speed.

• 한국정보통신학회논문지
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• 제26권9호
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• pp.1367-1373
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• 2022

본 논문에서는 셀프리 다중안테나 네트워크에서 하위 성능 사용자의 주파수 효율을 증대시키기 위한 전력 재할당 기법을 고려한다. AP(Access Point)는 사용자의 대규모 페이딩(large-scale fading) 채널 정보를 이용해 채널 세기에 비례하여 전력을 할당하여 전체 네트워크의 전력효율을 극대화한다. 다음으로 AP는 하위 성능 사용자의 주파수 효율을 증가시키기 위해 할당전력 중 임계비율 이상의 전력을 할당받은 사용자의 전력을 임계비율과 같아지도록 줄이고, 회수한 전력을 채널이 가장 나쁜 사용자에게 추가로 할당한다. 시뮬레이션을 통해 전력 재할당 기법을 통해 증가시킬 수 있는 하위 성능 사용자의 주파수 효율을 정량적으로 검증한다.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.104-110
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• 2006

오늘날 시스템 온 칩 테스트에 있어서 많은 양의 테스트 데이터, 시간 및 전력 소모는 매우 중요한 문제이다. 이러한 문제들을 해결하기 위해서 본 논문은 새로운 테스트 데이터 압축 기술을 제안한다. 우선, 테스트 큐브 집합에 있는 돈 캐어 비트에 저전력 테스트를 위한 비트할당을 한다. 그리고, 비트할당이 된 저전력 테스트 데이터의 압축효율을 높이기 위해 이웃 비트 배타적 논리합 변환을 사용하여 변환한다. 최종적으로, 변환된 테스트 데이터는 효과적으로 압축됨으로써 테스트 장비의 저장공간과 테스트 데이터 인가시간을 줄일 수 있게 된다.