• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권2호
• /
• pp.118-129
• /
• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• ETRI Journal
• /
• 제23권2호
• /
• pp.77-84
• /
• 2001

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.

• 전기전자학회논문지
• /
• 제5권1호
• /
• pp.52-58
• /
• 2001

본 논문에서는 입력이 TTL 전압 레벨일 때 저전력으로 동작하도록 설계된 TTL-to-CMOS 입력버퍼의 회로를 제안한다. 회로 구성은 내부 활성 클럭펄스로 제어되는 반전형 입력버퍼와 래치로 구성하고, 직류 단락전류를 제거하기 위해 클럭펄스가 로우상태일 때는 입력버퍼가 동작되지 않도록 하고 하이일 때만 정상적으로 동작되도록 하였다. 시뮬레이션을 수행한 결과 제안된 회로의 전력-지연 곱이 하나의 입력당 33.7% 줄어듬을 확인하였다.

• Journal of Astronomy and Space Sciences
• /
• 제13권2호
• /
• pp.52-66
• /
• 1996

본 논문에서는 우리별 2호(KITSAT-2)와 같은 소형위성의 실시간 제어 컴퓨터 시스댐인 KASCOM(KAIST satellite computer)의 설계시 요구사항(requirement)파 설계 방식(design meth-odology)을 제시한다. 위성 컴퓨터는 위성의 서브시스템으로서 뿐만 아니라 위성의 관리 제어 및 실험 장치들의 운용에 이르기까지 위성의 전 시스템파 연관을 맺고 었다. 이러한 연관성 때문에 위성 컴퓨터의 신뢰성은 위성의 전체 생명 유지에 매우 중요하다. 위성의 제어 컴퓨터로서 가져야 할 요구조건은 위성의 실시간 제어를 위한 연산 능력, 결함 허용의 입출력 시스템, 저전력소모, 무게, 크기, 방사선 차폐 등이다. 이러한 요구조건을 만족시키기 위해 KASCOM에 채택된 여러 설계 방법이 소개된다. 설계뿐만 아니라 실수 없이 구현하고 성능 및 환경 시험을 하는 것도 매우 중요하다. KASCOM의 구현 및 테스트 역시 본 논문에서 다툰다. 마지막으로 구현된 시스템의 실제 운용(in-orbit) 결파를 제시한다. 운용 결과, 프로그램 메모리(lMbit SRAM)에서는 하루 평균 2개의 SEU(lMbyte 당), 데이터 메모리(4Mbit SRAM)에서는 하루 평균 3.7개의 SEU(l Mbyte 당)가 관측되었다. 따라서 저집적 메모리가 고집적 메모리보다 SEU에 강한 것으로 보여진다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2005년도 ICCAS
• /
• pp.1826-1829
• /
• 2005

Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제13권4호
• /
• pp.1922-1940
• /
• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.

• 대한전자공학회논문지SD
• /
• 제44권3호
• /
• pp.26-34
• /
• 2007

본 논문에서는 신체 임피던스 측정법(Bioelectrical Impedance Analysis, 이하 BIA)을 기초로 한 체지방 측정 칩 설계에 대한 내용을 서술하였다. 제안된 회로는 인체에 전류 신호를 인가하는 회로, 인체를 통해 나온 전압 신호를 측정하는 회로, 회로의 동작을 제어하는 마이크로 콘트롤러(Micom), 그리고 분석프로그램이 내장된 메모리(SRAM, EEPROMs) 의 모든 기능을 하나의 칩에 집적하였다. 특히 정밀한 인체 임피던스 측정을 위하여 다주파수 동작이 가능한 대역통과필터(Band Pass Filter, BPF)를 설계하였다. 또한, 설계된 대역통과필터는 weak inversion 영역에서 동작하기 때문에 면적과 전력소모를 줄일 수 있었다. 그리고 측정부분 회로의 성능을 개선하기 위해서 차동차이증폭기(Differential difference amplifier, DDA)를 이용한 새로운 전파정류기(Full wave rectifier, FWR)를 설계하였다. 또한 이 회로는 마지막 단에 연결될 아날로그-디지털 변환기(ADC)의 설계에 대한 부담을 덜어주는 장점도 있다. 이 칩의 시제품은 CMOS 0.35um 공정을 이용하였고 전력소모는 모든 주파수에서 6mW 이며 전원전압은 3.3V이다. 전체 칩의 크기는 $5mm\times5mm$ 이다.

• 대한임베디드공학회논문지
• /
• 제10권6호
• /
• pp.391-397
• /
• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• 반도체디스플레이기술학회지
• /
• 제20권4호
• /
• pp.10-15
• /
• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• 한국멀티미디어학회논문지
• /
• 제19권7호
• /
• pp.1179-1187
• /
• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.