• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.391-397
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• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.232-234
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• 1996

The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.41-46
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• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.