• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.265-268
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• 2001

In this paper we investigate the implementation cost of value prediction methods for high performance micro-processors, and propose a new value prediction microarchitecture with low cost. After simulation, we found that the proposed microarchitecture can decrease the implementation cost by 36% to 50% and with slight performance degradation (less than 5%) .

• 한국디지털정책학회:학술대회논문집
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• 한국디지털정책학회 2006년도 추계학술대회
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• pp.409-418
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• 2006

The purpose of this paper is to present a low cost u-City portal development idea and to propose an exclusive system architecture using 3-D interface layers. 3-D interface layers consist of reused ideas of data from existed public data produced from GIS in order to reduce Produce Processes. 3-D interface layers implement a u-City portal systems that tags from physical spaces 1 ink to mobiles from ubiquitous networks between electronic spaces and physical spaces. Primary produce of this study exhibits an exclusive architecture of a u-City portal for speedy and low cost web 3-D interface layers and GIS data, and for implementation interface of 3-D types on USN of physical spaces. Secondary produce of this study represents that a 3-D u-City portal system has visualized speedy implementation characteristics for implementation of the application systems to execute an ubiquitous concept by returning electronic space to physical space, and to present the low cost 3-D u-City portal than an existed 3-D u-city development strategy. Therefore continuous expansion and study of the 3-D interface physical space under a 상황인지(Context Awareness)ubiquitous will appear the innovated u-City portal systems.

• IEIE Transactions on Smart Processing and Computing
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• 제1권2호
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• pp.95-105
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• 2012

The widespread implementation of RFID in ubiquitous computing is constrained considerably by privacy and security unreliability of the wireless communication channel. This failure to satisfy the basic, security needs of the technology has a direct impact of the limited computational capability of the tags, which are essential for the implementation of RFID. Because the universal application of RFID means the use of low cost tags, their security is limited to lightweight cryptographic primitives. Therefore, EPCGen2, which is a class of low cost tags, has the enabling properties to support their communication protocols. This means that satisfying the security needs of EPCGen2 could ensure low cost security because EPCGen2 is a class of low cost, passive tags. In that way, a solution to the hindrance of low cost tags lies in the security of EPCGen2. To this effect, many lightweight authentication protocols have been proposed to improve the privacy and security of communication protocols suitable for low cost tags. Although many EPCgen2 compliant protocols have been proposed to ensure the security of low cost tags, the optimum security has not been guaranteed because many protocols are prone to well-known attacks or fall short of acceptable computational load. This paper proposes a remedy protocol to the flyweight RFID authentication protocol proposed by Burmester and Munilla against a desynchronization attack. Based on shared pseudorandom number generator, this protocol provides mutual authentication, anonymity, session unlinkability and forward security in addition to security against a desynchronization attack. The desirable features of this protocol are efficiency and security.

• 전자공학회논문지B
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• 제32B권10호
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• pp.1338-1346
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• 1995

In this paper, we suggest the implementation of a DGPS system using two low cost commercial C/A code GPS modules and modems and its efficient operational techniques to provide DGPS service which guarantees the position accuracy of better than 10 meters for more users. The proposed DGPS system can be implemented easil at low cost because it needs a GPS module and a modem for each reference station and user. The reference station makes plans of the receiving schedule from the satellite set at each period and then provides the correction data for various satellite sets in a period. The main contribution of this paper is that users can utilize the correction data continuously and efficiently through the recursive least squares lattice filtering method. Experimental results show the position accuracy of better than 10 meters using the suggested DGPS system in almost real time.

• 정보통신설비학회논문지
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• 제8권1호
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• pp.24-29
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• 2009

In this paper, we show the implementation of the low-cost RF transceiver module for parking control system. Super regenerative receiver scheme was adopted for this module due to its simplicity, low-cost, low power consumption and small number of components to improve reliability of the systems. For improving communication error rate by collision and in-band noise, dual-channel hopping scheme was adopted. Testing prototypes under the environment of simultaneous transmissions, we verified that the designed scheme is able to improve the success rate of data transmission of wireless parking control system cost effectively.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1984년도 추계학술발표회논문집
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• pp.98-100
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• 1984

This paper design the emulator of the 8 bit microprocessor based on the z-80. The system control the debugging relation ship concerning the hardware and the software between the target system and the host system. It is purpose that emulator manufacture low cost.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.253-256
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• 2000

This paper describes a DSP implementation of a real-time 3D sound localization algorithm with the use of a low power embedded DSP. A distinctive feature of this implementation is that the audible frequency band is divided into three, in accordance with the sound reflection and diffraction phenomena through different media from a certain sound source to human ears, and then in each subband a specific implementation procedure of the 3D sound localization is devised so as to operate real-time at a low frequency of 50MHz on a 16bit fixed-point DSP. Thus out DSP implementation can provide a listener with 3D sound effects through a headphone at low cost and low power consumption.

• 대한전자공학회논문지SD
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• 제41권12호
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• pp.67-74
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• 2004

AES는 인터넷 프로토콜의 대칭키 보안 알고리즘으로 널리 사용된다. 무선 내장형 시스템들이 점점 더 전통적인 유선 네트워크 프로토콜을 많이 사용하고 있으므로 이들 무선 내장형 시스템을 위한 저비용 AES 알고리즘 구현은 매우 중요하다. 가장 기본적인 AES 아키텍처는 키 스케줄을 포함하여 20개의 S-box를 사용하는 하나의 cipher 라운드로 구성되어 있다. 암호화는 동일한 라운드를 반복하여 완료된다. 근래에 이 방법의 구현 비용을 더욱 줄이기 위하여 오직 8개의 S-box만 사용하는 folded architecture가 제안되었다. 본 논문에서는 folded architecture를 이용하여 무선 통신 기술을 위한 저비용 AES 구현 구조에 대하여 연구한다. 먼저 folded architecture를 개선하여 16 바이트의 추가적인 상태 메모리 사용을 줄였다. 구현 비용을 더욱 줄이기 위하여 데이터 암호화에 하나의 S-box만 사용하는 single byte architecture를 구현하였다. Single byte architecture는 암호화에 352 클록이 소요된다. FPGA 구현 시 최대 동작 주파수는 40MHz에 도달하였다. 따라서 암호화 속도는 13Mbps 이상으로 3G 무선통신에 충분하다.

• 전자공학회논문지B
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• 제32B권10호
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• pp.1314-1325
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• 1995

In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.

• 제어로봇시스템학회논문지
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• 제21권2호
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• pp.168-172
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• 2015

In general, open-loop fiber-optic gyroscopes (FOG) are less stable than closed-loop FOGs but they offer simpler implementation. The typical operation time of line-of-sight (LOS) stabilization systems is a few seconds to one hour. In this paper, a open-loop fiber optic gyroscope (FOG) for LOS applications is designed and implemented. The design goal is aimed at implementing a low cost, compact FOG with low Angle Random Walk (ARW) (< $0.03deg/\sqrt{h}$) and bias instability (< 0.25deg/h). The FOG uses an open-loop all-fiber configuration with 100M PM fiber wound on a small diameter spool. In order to get the design goal, digital signal processing techniques for signal detection, modulation control and compensation are designed and implemented in FPGA.