• Journal of Information Processing Systems
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• v.5 no.2
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• pp.105-116
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• 2009

To solve the general problems surrounding the application of genetic algorithms in stereo matching, two measures are proposed. Firstly, the strategy of simplified population-based incremental learning (PBIL) is adopted to reduce the problems with memory consumption and search inefficiency, and a scheme for controlling the distance of neighbors for disparity smoothness is inserted to obtain a wide-area consistency of disparities. In addition, an alternative version of the proposed algorithm, without the use of a probability vector, is also presented for simpler set-ups. Secondly, programmable graphics-hardware (GPU) consists of multiple multi-processors and has a powerful parallelism which can perform operations in parallel at low cost. Therefore, in order to decrease the running time further, a model of the proposed algorithm, which can be run on programmable graphics-hardware (GPU), is presented for the first time. The algorithms are implemented on the CPU as well as on the GPU and are evaluated by experiments. The experimental results show that the proposed algorithm offers better performance than traditional BMA methods with a deliberate relaxation and its modified version in terms of both running speed and stability. The comparison of computation times for the algorithm both on the GPU and the CPU shows that the former has more speed-up than the latter, the bigger the image size is.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.749-755
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• 2003

Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.

• International Journal of Aeronautical and Space Sciences
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• v.11 no.4
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• pp.338-344
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• 2010

This paper discusses the development of the control system of a mini quadrotor in Konkuk University for indoor applications. The attitude control system consists of a stability augmentation system, which acts as the inner loop control, and a modern control approach based on modeling will be implemented as the outer loop. The inner loop control was experimentally satisfied by a proportional-derivative controller; this was used to support the flight test in order to validate the modeling. This paper introduces the mathematical model for the simulation and design of the optimal control on the outer loop control. To perform the experimental tests, basic electronic hardware was developed using simple configurations; a microcontroller used as the embedded controller, a low-cost 100 Hz inertial sensors used for the inertial sensing, infra-red sensors were employed for horizontal ranging, an ultrasonic sensor was used for ground ranging and a high performance propeller system built on an quadrotor airframe was also employed. The results acquired from this compilation of hardware produced an automatic hovering ability of the system with ground control system support for the monitoring and fail-safe system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.779-780
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• 2015

As IoT becomes a main technology of the age, many IoT products have developed and are being developed now. By using open-source hardware "Arduino"and open-source IoT platform "Temboo" to analize CAN signal from vehicle and make vehicle IoT environment to analize and use it through the mobile phone, figured out the way to develop the IoT environment with low cost. Also suggest the way to solve problems and improove.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.157-163
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• 2014

This paper proposes a two-stage step-down buck and a tapped-inductor boost cascaded converter for high efficiency photovoltaic micro-inverter applications. The proposed inverter is a new structure to inject a rectified sinusoidal current into a low-frequency switching inverter for single-phase grid with unity power factor. To build a rectified-waveform of the output current. the converter employs both of a high efficiency step-up and a step-down converter in cascade. In step-down mode, tapped inductor(TI) boost converter stops and the buck converter operates alone. In boost mode, the TI converter operates with the halt of buck operation. The converter provides a rectified current to low frequency inverter, then the inverter converts the current into a unity power-factor sinusoidal waveform. By applying a TI, the converter can decrease the turn-on ratios of the main switch in TI boost converter even with an extreme step-up operation. The performance validation of the proposed design is confirmed by an experimental results of a 120W hardware prototype.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.431-442
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• 2010

Because embedded system is combined system of hardware and software, we should design by considering elements such as real-time, reactive, small size, low weight, safe, reliable, harsh environment, low cost, and so on. However, those are poorly reflected on current embedded system development. Especially, there is few existed framework-based embedded system development. As a result, there are many internal codes which is not related with system operation in currently developed embedded system, and reusability or variability is not considered into embedded system development. Therefore we propose a formal specification technique using Z language to guarantee completeness or consistency of design of reusability framework proposed for improving reusability of embedded system. Also we assure correctness of framework design by checking Z model through Z-Eves Tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.137-141
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• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.6
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• pp.556-563
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• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).