• Journal of Communications and Networks
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• 제17권4호
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• pp.346-350
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• 2015

It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

• Journal of Information Processing Systems
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• 제15권2호
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• pp.271-287
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• 2019

The synchronization scheme based on moving average is robust and suitable for the same rule to be adopted in embedding watermark and synchronization code, but the imperceptibility and search efficiency is seldom reported. The study aims to improve the original scheme for robust audio watermarking. Firstly, the survival of the algorithm from desynchronization attacks is improved. Secondly, the scheme is improved in inaudibility. Objective difference grade (ODG) of the marked audio is significantly changed. Thirdly, the imperceptibility of the scheme is analyzed and the derived result is close to experimental result. Fourthly, the selection of parameters is optimized based on experimental data. Fifthly, the search efficiency of the scheme is compared with those of other synchronization code schemes. The experimental results show that the proposed watermarking scheme allows the high audio quality and is robust to common attacks such as additive white Gaussian noise, requantization, resampling, low-pass filtering, random cropping, MP3 compression, jitter attack, and time scale modification. Moreover, the algorithm has the high search efficiency and low false alarm rate.

• 한국통신학회논문지
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• 제33권10C호
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• pp.798-804
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• 2008

본 논문에서는 마이크로프로세서의 영상 정보 처리 시 L2 캐시의 오류검출 및 정정 회로의 저 전력을 구현하기 위한 오류정정 회로를 제안 하였다. 영상 정보 처리 시에 마이크로프로세서의 L2 캐시에 접근하는 입출력 데이터를 분석하기 위하여 Simplescalar-ARM 사용하여 데이터 입출력에 대한 빈도와 32 bit 처리를 위한 각 bit에 대한 변화율에 대해서 분석한다. 변화량이 많은 비트와 변화량이 적은 비트를 추출하고, 변화의 유사성을 가지는 비트들의 배치를 고려하여 저 전력을 구현할 수 있는 H-matrix를 제안하고 회로를 구현한다. H-spice를 이용하여 구현된 회로와 기존 마이크로프로세서에서 사용하는 Odd-weight-column code의 전력소모에 대한 비교를 위하여 시뮬레이션을 수행하였다. 실험결과 Odd-weight-column code 대비 17%의 소비전력을 감소시킬 수 있었다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.189-192
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• 2000

In this paper, we consider a code acquisition of W-CDMA signals over multipath Rayleigh fading channel when double-dwell serial search code acquisition is used for initial synchronization. We derive the detection and false alarm probability, and mean acquisition time mathematically by taking into account of multiple H$\_$l/ cells and double-dwell serial search. It is noteworthy that the more the number of the post-detection integration, the shorter the mean acquisition time in low SNR.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.77-80
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• 2000

Adaptive filter based code acquisition scheme offers a fast acquisition with a low error probability. However, it has been studied only under a coherent environment. In this paper, the noncoherent adaptive code acquisition scheme employing a differential detection technique is proposed. For the proposed scheme, system probabilities and the mean acquisition time are analyzed numerically. Simulation results show that the proposed system outperforms over the conventional matched filter by 2-4 ㏈ under AWGN channel for 16 taps.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
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• pp.233-236
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• 2000

In this paper, we consider a code acquisition of W-CDMA signals over multipath Rayleigh fading channel when double-dwell serial search code acquisition is used for initial synchronization. We derive the detection and false alarm probability, and mean acquisition time mathematically by taking into account of multiple H$_1$ cells and double-dwell serial search. It is noteworthy that the more the number of the post-detection integration, the shorter the mean acquisition time in low SNR.

• 정보처리학회논문지A
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• 제14A권1호
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• pp.31-38
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• 2007

주어진 입력 프로그램과 의미적으로 동등하면서 좀 더 효율적인 코드로 바꾸는 것을 코드 최적화라 하며, 이런 과정은 코드 최적화기예 의해 수행된다. 본 논문에서는 코드 최적화기를 자동적으로 생성하는 도구인 코트 최적화긴 생성기를 설계하고 구현하였다. 즉 패턴 형식에 대한 표현을 입력으로 받아 기술된 형태의 최적화 코드를 찾아내는 DFA 패턴 매칭을 위한 코드 최적화기를 자동적으로 생성하는 것이다. DFA 패턴 매칭은 패턴들의 정규화 과정을 통해 패턴 검색 시 발생하는 중복 비교를 제거하여, 패턴 형태의 단순화 및 구조를 개선함으로 비용이 적게든다. DFA 패턴 매칭을 위한 코드 최적화기의 자동적 생성은 다양한 형태의 중간코드로 바뀌더라도 해당하는 코트 최적화기를 만들어야 하는 수고를 덜어줌으로써 코드 최적화에 대한 정형화(formalism)를 할 수 있다. 또한, DFA로 구성되어 최적화를 하기 때문에 최적화 속도가 빠르고, 코드 최적화기를 만드는데 필요한 시간과 비용을 절약할 수 있는 장점을 가진다.

• ETRI Journal
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• 제39권3호
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• pp.319-325
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• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• Journal of information and communication convergence engineering
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• 제4권2호
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• pp.75-78
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• 2006

This work presents a low complexity maximum-likelihood decoder for signal detection in VBLAST-STBC system, which employs non-square O-STBC code rate 3/4. Stacking received symbols from different symbol duration and applying QR decomposition result in the special format of upper triangular matrix R so that the proposed decoder is able to provide not only ML-like BER performance but also very low computational load. The low computational load and ML-like BER performance properties of the proposed decoder are verified by computer simulations.