• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.442-446
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• 2003

This paper proposes a new two-stage two-phase VPP charge pump configured in such a manner that body effect and the threshold voltage loss are eliminated. The newly proposed circuit is fabricated using 0.18um triple-well CMOS process and the measurement result shows that the VPP level tracks 3VDD when VDD is above the threshold voltage.

• Proceedings of the IEEK Conference
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• summer
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• pp.74-76
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• 2004

A Half-VDD Voltage(VHDD) Generator using PMOS pull-up transistor and NMOS pull-down transistor was newly proposed for low-voltage DRAMs. The driving current was increased and the power-on settling time was reduced in the new circuit. The newly proposed VHDD generator worked successfully at VDD at 1.5V and fabricated using 0.18um CMOS twin-well technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.996-1002
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• 2000

Ferroelectric (Ba, Sr) TiO$_3$(BST) thin films have attracted much attention for use in new capacitor materials of dynamic random access memories (DRAMs). In order to apply BST to the DRAMs, the etching process for BST thin film with high etch rate and vertical profile must be developed. However, the former studies have the problem of low etch rate. In this study, in order to increase the etch rate, BST thin films were etched with a magnetically enhanced inductively coupled plasma(MEICP) that have much higher plasma density than RIE (reactive ion etching) and ICP (inductively coupled plasma). Experiment was done by varying the etching parameters such as CF$_4$/(CF$_4$+Ar) gas mixing ratio, rf power, dc bias voltage and chamber pressure. The maximum etch rate of the BST films was 170nm/min under CF$_4$/CF$_4$+Ar) of 0.1, 600 W/-350 V and 5 mTorr. The selectivities of BST to Pt and PR were 0.6 and 0.7, respectively. Chemical reaction and residue of the etched surface were investigated with X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.2
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• pp.18-22
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• 2001

The thin films of high permitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)TiO$_3$ thin as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Sio$_2$/Si substrate at 4,000 [rpm] for 10 seconds. The structural characteristics of the surface were analyzed by fractal dimension. The thickness of BST ceramics thin films was about 260∼280 [nm]. The property of the leakage current was stable with 10-9∼10-11[A] when the applied voltage was 0∼3[V]. BST thin films ha low leakage current properties when fractal dimension was low and a coating area was high.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.163-166
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• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.