• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.222-222
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• 2010

Transparent semiconductor oxide thin films have been attracting considerable attention as potential channel layers in thin film transistors (TFTs) owing to their several advantageous electrical and optical characteristics such as high mobility, high stability, and transparency. TFTs with ZnO or similar metal oxide semiconductor thin films as the active layer have already been developed for use in active matrix organic light emitting diode (AMOLED). Of late, there have been several reports on TFTs fabricated with InZnO, AlZnSnO, InGaZnO, or other metal oxide semiconductor thin films as the active channel layer. These newly developed TFTs were expected to have better electrical characteristics than ZnO TFTs. In fact, results of these investigations have shown that TFTs with the new multi-component material have excellent electrical properties. In this work, we present TFTs with inverted coplanar geometry and with a novel HfInZnO active layer co-sputtered at room temperature. These TFTs are meant for use in low voltage, battery-operated mobile and flexible devices. Overall, the TFTs showed good performance: the low sub-threshold swing was low and the $I_{on/off}$ ratio was high.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• International Journal of Industrial Entomology and Biomaterials
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• v.29 no.2
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• pp.153-161
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• 2014

The aim of this study is to investigate the effects of ambient thermal environments on the development of swallowtail butterflies (Sericinus montela Gray). Developmental durations and survival rates of S. montela were examined at two crucial developmental stages, embryonic and larval development, at varying temperatures ranging from $15^{\circ}C$ to $35^{\circ}C$. As expected, our results indicated that increasing temperatures decreased the developmental duration and survival rate of the eggs. However, the larvae and pupae showed maximum survival rates at $20.0^{\circ}C$ and $25.0^{\circ}C$, and the represented durations were similar to those of the eggs. Larval development was stage-specific, revealing that the fourth and fifth instars at the later stages were more susceptible to temperature variation. When considering both parameters, the optimal development of S. montela occurred within the temperature range of $20.0-25.0^{\circ}C$. The lower threshold for the complete development of S. montela from eggs to eclosion of adults was calculated at $10.6^{\circ}C$ by linear regression analysis. The estimated value is similar to that of other endemic insects distributed in temperate climate zones, which indicates that S. montela belongs to a small group of swallowtails adjusted to low ambient temperatures. From the results, we predict that the full development of S. montela could be achieved within the temperature range of $17.5-30.0^{\circ}C$. Embryonic development ceased at both test temperature extremes, and no further larval development proceeded after the third instar at $35.0^{\circ}C$. These results suggest that embryogenesis can be significantly influenced by slight variations in the ambient thermal environment that fall below the optimal range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.63-63
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• 2009

Many researchers have been studied as active and transparent electrode using ZnO (Zinc oxide) inorganic semiconductor material due to their good properties such as wide band-gap and high electrical properties compared with amorphous-Si. In this study, we fabricated ZnO films by the RF magnetron sputtering method at a low temperature for a channel layer in thin-film transistor (TFT) and investigated the characteristics of sputtered ZnO films. Also, the electrical properties of TFT using ZnO channel layer such as field effect mobility(${\mu}$), threshold voltage ($V_{th}$), and $I_{on/off}$ ratio are investigated for the application of the display and electronic devices.

• Electrical & Electronic Materials
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• v.9 no.2
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• pp.174-179
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• 1996

We present a new physically based analytical equation for electron effective mobility in MOS inversion layers. The new semi-empirical model is accounting expicitly for surface roughness scattering and screened Coulomb scattering in addition to phonon scattering. This model shows excellent agreement with experimentally measured effective mobility data from three different published sources for a wide range of effective transverse field, channel doping and temperature. By accounting for screened Coulomb scattering due to doping impurities in the channel, our model describes very well the roll-off of effective mobility in the low field (threshold) region for a wide range of channel doping level (Na=3.0*10$^{14}$ - 2.8*10$^{18}$ cm$^{-3}$ ).

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1297-1300
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• 2008

Electrical stress degradation of low temperature, amorphous silicon thin film transistors is reviewed, and the implications for various types of flexible circuitry including active matrix backplanes, integrated drivers and general purpose digital circuitry are examined. A circuit modeling tool that enables the prediction of complex circuit degradation is presented.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.239-242
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• 2008

We have investigated the reliability of short channel ($L=1.5{\mu}m$) p-type ELA poly-Si TFTs under hot carrier stress. Threshold voltage of short channel TFT was significantly more shifted to positive direction than that of long channel TFT under the same stress. This result may be attributed to electron trapping at the interface between poly-Si film and gate oxide layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.605-608
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• 2006

The recent application of wide band gap oxide semiconductors to transparent thin film transistors (TTFTs) is making a fast and growing (r)evolution on the contemporary solid-state electronics. In this paper we present some of the recent results we have obtained using wide band gap oxide semiconductors, like indium zinc oxide, produced by rf sputtering at room temperature. The devices work in the enhancement mode and exhibit excellent saturation drain currents. On-off ratios above $10^6$ are achieved. The optical transmittance data in the visible range reveals average transmittance higher than 80 %, including the glass substrate. Channel mobilities are also quite respectable, with some devices presenting values around $25\;cm^2/Vs$, even without any annealing or other post deposition improvement processes. The high performances presented by these TTFTs associated to a high electron mobility, at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and a low threshold voltage, opens new doors for applications in flexible, wearable, disposable portable electronics as well as battery-powered applications.