• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.169-176
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• 2017

This paper presents research on low-voltage microgrids to maintain a continuous power supply to critical loads on grid-connected islands in Korea. The low-voltage microgrids of this paper focused on that changes public office buildings into uninterrupted microgrids by autonomous operation. For this, a microgrid controller (MGC) and a power conditioning system (PCS) that allow a seamless transfer between grid-connected and grid-isolated operation are proposed. The proposed PCS operates with a silicon controlled rectifier (SCR) switch and employs a simple structure. It supplies power continuously without operators through a coordinated operation between MGC and PCS. In addition, proposed MG has a schedule operation for minimizing electricity charges and provides ancillary services that enable the utilization of resources according to the operation purpose of utility distribution networks. To demonstrate the uninterrupted low-voltage microgrid proposed in this study, a microgrid was implemented and tested in a public office building in Anjwa Island, Jeollanam-do in Korea. A seamless, autonomous operation history, despite system disturbances, was obtained through a long-term demonstration of operation. The results showed that the proposed microgrid technology can be used to achieve energy resilience in grid-connected island areas.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.738-744
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• 2018

This paper proposes a low cost hot swap operation circuit of a parallel operation power supply for servers. Hot swap function for server power system is essential in 24 hour operation system such as internet data center, server, factory and etc. Server power supplies used in internet data centers have two or more parallel operations with the hot swap operation. However, the cost of the power supply is high because the controller IC for hot swap operation is very expensive. Therefore, this paper proposes a parallel-operated power supply with a low-cost hot swap controller for servers. The proposed system can operate hot swap function by using discrete devices and reduce the cost by more than 50%. A 1.2kW prototype system is implemented to verify the proposed low cost hot swap controller.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.587-592
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• 2015

According to increase in the use of the LED, the demand for low power consumption LED display design of the controller block has increased. In this paper, the low power LED controller block was designed through the power source supply that leads adiabatic operation from constant current source circuit operated by digital signal control. The proposed circuit was implemented using a 0.35um CMOS process. and it demonstrated linear operation of the circuit. From the simulation result, the proposed circuit was evaluated with about 82% power consumption reduction effect in comparison with conventional LED controller block. This research is expected to be helpful for the low power operation and the solution for heat problem of LED display.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• ETRI Journal
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• v.27 no.3
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• pp.312-318
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• 2005

Mid-span spectral inversion (MSSI) has to utilize high optical pump power, for its operation principle is based on a nonlinear optical wavelength conversion. In this paper, a low pump-power operation of MSSI-based chromatic dispersion compensation (CDC) has been achieved successfully, for the first time to our knowledge, by introducing a noise pre-reduction scheme in cascaded wavelength conversions with periodically poled $LiNbO_3$ waveguides at a relatively low operation temperature. As preliminary studies, phase-matching properties and operation-temperature dependence of the wavelength converter (WC) were characterized. The WC pumped at 1549 nm exhibited a wide conversion bandwidth of 59 nm covering the entire C-band and a conversion efficiency of -23.6 dB at 11 dBm pump power. CDC experiments were implemented with 2.5 and 10 Gb/s transmission systems over 100 km single-mode fiber. Although it is well-known that the signal distortion due to chromatic dispersion is not critical at a 2.5 Gb/s transmission, the clear recovery of eye patterns was identified. At 10 Gb/s transmission experiments, eye patterns were retrieved distinctly from seriously distorted ones, and notable improvements in bit-error rates were acquired at a low pump power of 14 dBm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.583-584
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• 2008

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.7
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• pp.363-368
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• 1999

The parallel operation system of multiple uninterruptible power supplies(UPSs) is used to increase power capacity of the system or to secure higher reliability at critical loads. In the parallel operation of the two UPSs, the load-sharing control to maintain the current balance between them is a key technique. Because a UPS has low output impedance and quick response characteristics, in case of an unbalanced load inverter output current changes very rapidly and thereby can instantaneously reach an overload condition. In this study, high precise load-sharing controller is proposed and implemented for the parallel operation system of two UPSs with low impedance characteristics and this controller controls the frequency and the voltage to minimize the active power component and the reactive power component which are gotten from the current difference between two UPSs. And then a good performance of the proposed method is verified by experiments in the parallel operation system with two 40KVA UPSs.

• Nuclear Engineering and Technology
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• v.53 no.9
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• pp.2888-2898
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• 2021

Vital area identification (VAI) is an essential procedure for the design of physical protection systems (PPSs) for nuclear power plants (NPPs). The purpose of PPS design is to protect vital areas. VAI has been improved continuously to overcome the shortcomings of previous VAI generations. In first-generation VAI, a sabotage fault tree was developed directly without reusing probabilistic safety assessment (PSA) results or information. In second-generation VAI, VAI model was constructed from all PSA event trees and fault trees. While in third-generation VAI, it was developed from the simplified PSA event trees and fault trees. While VAIs have been performed for NPPs in full-power operations, VAI for NPPs in low-power and shutdown (LPSD) operations has not been studied and performed, even though NPPs in LPSD operations are very vulnerable to sabotage due to the very crowded nature of NPP maintenance. This study is the first to research and apply VAI to LPSD operation of NPP. Here, the third-generation VAI method for full-power operation of NPP was adapted to the VAI of LPSD operation. In this study, LPSD VAI for a few plant operational states (POSs) was performed. Furthermore, the operation strategy of vital areas for both full-power and LPSD operations was discussed. The LPSD VAI method discussed in this paper can be easily applied to all POSs. The method and insights in this study can be important for future LPSD VAI that reflects various LPSD operational states. Regulatory bodies and electric utilities can take advantage of this LPSD VAI method.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.