• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.608-611
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• 2003

A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.97-114
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• 2022

Interest is increasing in electrocardiogram (ECG) signal analysis for embedded devices, creating the need to develop an algorithm suitable for a low-power, low-memory embedded device. Linear approximation of the ECG signal facilitates the detection of fiducial points by expressing the signal as a small number of vertices. However, dynamic programming, a global optimization method used for linear approximation, has the disadvantage of high complexity using memoization. In this paper, the calculation area and memory usage are improved using a linear approximated template. The proposed algorithm reduces the calculation area required for dynamic programming through local optimization around the vertices of the template. In addition, it minimizes the storage space required by expressing the time information using the error from the vertices of the template, which is more compact than the time difference between vertices. When the length of the signal is L, the number of vertices is N, and the margin tolerance is M, the spatial complexity improves from O(NL) to O(NM). In our experiment, the linear approximation processing time was 12.45 times faster, from 18.18 ms to 1.46 ms on average, for each beat. The quality distribution of the percentage root mean square difference confirms that the proposed algorithm is a stable approximation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.10-15
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• 2012

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

• The Journal of the Acoustical Society of Korea
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• v.38 no.1
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• pp.9-22
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• 2019

In this paper, we propose a method that can be applied to the efficient implementation of multi-channel active noise controller. Since the normalized MFxLMS (Modified Filtered-x Least Mean Square) algorithm for the multi-channel active noise control requires a large amount of computation, the difficulty has lied in implementing the algorithm using a low-cost MCU (Microcontoller Unit). We implement the multi-channel active noise controller efficiently by optimizing the software based on the features of the MCU. By maximizing the usage of single-cycle MAC (Multiply- Accumulate) operations and minimizing move operations of the delay memory, we can achieve more than 3 times the performance in the aspect of computational optimization, and by parellel processing using the auxillary processor included in the MCU, we can also obtain more than 4 times the performance. In addition, the usage of additional parts can be minimized by maximizing the usage of the peripherals embedded in the MCU.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.2
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• pp.361-371
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• 2017

The increase in user data stored in the device implies the increase in threats of users' sensitive data. Currently, smartphone authentication mechanisms such as Pattern Lock, fingerprint recognition are widely used. Although, there exist disadvantages of inconvenience use and dependence that users need to depend on their own memory. User behavior based authentication mechanism have advantages of high convenience by offering continuous authentication when using the mobile device. However, these mechanisms show limitations on low accuracy of authentication and there are researches to improve the accuracy. This paper proposes improved authentication mechanism that uses user's smartphone application usage pattern which has not considered on earlier studies. Also, we analyze performance of proposed mechanism with collected datasets from actual use of smartphone applications.

• Journal of IKEEE
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• v.24 no.3
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• pp.895-900
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• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.19 no.5
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• pp.523-529
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• 2009

Smart sensor is known as intelligent sensor, it is different with other conventional sensors in the case of intelligent system embedded on it. Smart sensor has many benefits e.g. low-cost in usage, self-decision and self-diagnosis abilities. This sensor consists of perception element(sensing element), signal processing and technology of communication. In this work, a bridge and structure of smart sensor has been investigated to be capable to condition monitoring routine. This investigation involves low power consumption, software programming, fast data acquisition ability, and authoritativeness warranty. Moreover, this work also develops smart sensor to be capable to perform high sampling rate, high resolution of ADC, high memory capacity, and good communication for data transfer. The result shows that the developed smart sensor is promising to be applied to various industrial fields.

• ETRI Journal
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• v.45 no.3
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• pp.433-447
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• 2023

Critical issues such as connection congestion, long transmission delay, and packet loss become even worse during epidemic, disaster, and so on. In this study, a link load balancing method is proposed to address these issues on the data plane, a plane of the software-defined network (SDN) architecture. These problems are NP-complete, so a meta-heuristic approach, discrete particle swarm optimization, is used with a novel hybrid cost function. The superiority of the proposed method over existing methods in the literature is that it provides link and switch load balancing simultaneously. The goal is to choose a path that minimizes the connection load between the source and destination in multipath SDNs. Furthermore, the proposed work is dynamic, so selected paths are regularly updated. Simulation results prove that with the proposed method, streams reach the target with minimum time, no loss, low power consumption, and low memory usage.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• The Journal of Korea Robotics Society
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• v.16 no.4
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• pp.327-335
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• 2021

In this paper, we propose an embedded robot system based on "ROS2 on Yocto" that can support various robots. We developed a lightweight OS based on the Yocto Project as a next-generation robot platform targeting cloud robotics. Yocto Project was adopted for portability and scalability in both software and hardware, and ROS2 was adopted and optimized considering a low specification embedded hardware system. We developed SLAM, navigation, path planning, and motion for the proposed robot system validation. For verification of software packages, we applied it to home cleaning robot and indoor delivery robot that were already commercialized by LG Electronics and verified they can do autonomous driving, obstacle recognition, and avoidance driving. Memory usage and network I/O have been improved by applying the binary launch method based on shell and mmap application as opposed to the conventional Python method. Finally, we verified the possibility of mass production and commercialization of the proposed system through performance evaluation from CPU and memory perspective.