• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.59 no.1
• /
• pp.18-23
• /
• 2010

As the increasing of Non-linear load, we have been growing interest for the harmonics. Harmonics has been focused on the current component rather than voltages. Voltage harmonics can be mainly generated at the PCC with non-linear load and act on voltage unbalance. Voltage harmonics can be enlarged at the capacitor with low impedance as frequency increases. Capacitor is basically used for the power-factor compensation and sometimes as the passive filter. Small voltage of low-order acts on quite a few at the capacitor by the current increase. Capacitor has easily fall under by harmonic components. In this paper, we measured the magnitude and phase angle of asymmetrical voltage with harmonics components at the PCC and calculated with the same condition. we concluded that voltage harmonics of higher order increase each current component but have a little effect on capacitor rating.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.2C no.6
• /
• pp.292-296
• /
• 2002

A new sustain driving method for the AC PDP is presented. In this driving method, the voltage source is connected to a storage capacitor, this storage capacitor charges an intermediate capacitor through LC resonance, and the panel is charged from the intermediate capacitor indirectly. In this way, the current flowing into the AC PDP when the sustain discharge occurs is reduced because the current is indirectly supplied from a capacitor, a limited source of charge. Thus, the input power to the output luminance efficiency is improved. Since the voltage supplied to the storage capacitor is doubled through LC resonance, this method call drive an AC PDP with a voltage source of about half of the voltage necessary in the conventional driving methods. The experiments showed that this charge-controlled driving method could drive ail AC PDP with a voltage source of as low as 107V. Using a panel of the conventional structure, luminous efficiency of 1.28 lm/W was achieved.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.1
• /
• pp.125-134
• /
• 2016

We propose an efficient high voltage level shifter for a high side Buck converter driving a light-emitting diode (LED) lamp. The proposed circuit is comprised of a low voltage pulse width modulation (PWM) signal driver, a coupling capacitor, a resistor, and a diode. The proposed method uses a property of a PWM signal. The property is that the signal repeatedly transits between a low and high level at a certain frequency. A low voltage PWM signal is boosted to a high voltage PWM signal through a coupling capacitor using the property of the PWM signal, and the boosted high voltage PWM signal drives a p-channel metal oxide semiconductor (PMOS) transistor on the high side Buck converter. Experimental results show that the proposed level shifter boosts a low voltage (0 to 20 V) PWM signal at 125 kHz to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.10
• /
• pp.1432-1441
• /
• 2012

In this study, an improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source inverter(Improved LCCT ZSI) with characteristics of Quasi Z-source inverter(QZSI) and LCCT Z-source inverter(LCCT ZSI) is proposed. The proposed inverter can also reduce the voltage stress and input current/capacitor voltage ripples compared with conventional LCCT ZSI and Quasi ZSI. A two winding trans in Z-impedance network of the conventional LCCT ZSI is replaced by a three winding trans in the proposed inverter. To verify the validity of the proposed inverter, a DSP controlled hardware was made and PSIM simulation was executed for each method. Comparing the current and voltage ripples of each method under the condition of input DC voltage 70[V] and output AC voltage 76[Vrms], the input current and capacitor voltage ripple factors of the proposed inverter were low as 11[%] and 1.4[%] respectively. And, for generation of the same output AC voltage of each method, voltage stress of the proposed inverter was low as 175[V] under the condition of duty ratio D=0.15. As mentioned above, we could know that the proposed inverter have the characteristics of low voltage stress, low ripple factor and low operation duty ratio compared with the conventional methods. Finally, the efficiency according to load change/duty ratio and the transient state characteristics were discussed.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.58 no.2
• /
• pp.148-153
• /
• 2009

As the increasing of non-linear load, we have a growing interest in power quality. Power quality has come to the voltage quality. Voltage harmonics consist in at the PCC by the non-linear load. Capacitor is generally used for the power compensation and as the passive filter by the serial connection with reactor. Capacitor has low impedance as the frequency increases, so easily fall down by the harmonic component of non-linear load. Small voltage of low-order acts on quite a few at the capacitor by the current increase. In this paper, we measured the magnitude and angle of voltage at the PCC and calculated under the same condition. we checked out that lower voltage of higher order produces current magnification.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.3
• /
• pp.134-141
• /
• 2006

A potential transformer(PT) has ratio error and phase angle error. Precise measurement of the errors of PT can be achieved using high voltage capacitance bridge, high voltage capacitor and low voltage capacitor. The uncertainty for this method is evaluated and found to be $20{\times}10^{-6}$ in both ratio error and phase angle error. The values measured for PT using the method are well consistent with the those measured for same PT in NMIA(National Measurement Institute of Australia) within the corresponding uncertainty.

• Journal of Power Electronics
• /
• v.7 no.4
• /
• pp.328-335
• /
• 2007

A conventional Single-Stage Power-Factor-Correction (PFC) AC/DC converter has a link capacitor voltage problem under high line input and low load conditions. In this paper, this problem is analyzed by using the voltage conversion ratio of the DC/DC conversion cell. By applying this analysis, a new Single-Stage PFC AC/DC converter with a boost PFC cell integrated with a Voltage-Doubler Rectified Asymmetrical Half-Bridge (VDRAHB) is proposed. The proposed converter features good power factor correction, low current harmonic distortions, tight output regulations and low voltage of the link capacitor. An 85W prototype was implemented to show that it meets harmonic requirements and standards satisfactorily with near unity power factor and high efficiency over universal input.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.2089-2091
• /
• 2000

Pulsed power systems consist of a capacitor bank, an isolated high-voltage charging power-supply, high-current bus-work for charging and discharging and a control system. In such pulsed power systems, the operating-lifetime of the capacitors is closely dependent on the voltage reversal. Hence, most capacitor-discharging systems includes crowbar circuits. The crowbar circuit prevents the capacitor recharging with reverse voltage. Usually it consists of crowbar resistors and high pulse-current diode-stacks connected in series. The requirements for the diode-stacks are fast-recovery time and high-voltage and large-current ratings, which results in the high cost of the pulsed-power system. This paper presents a protection scheme of a charging and discharging system of a 500kJ capacitor bank using a low-cost crowbar circuit and safety-fuses.

• Journal of information and communication convergence engineering
• /
• v.15 no.1
• /
• pp.62-71
• /
• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.586-589
• /
• 2012

In this paper, a tunable capacitor like an interdigital one is presented for low-voltage applications. In order to reduce operation voltage by enhancing fringing electric fields, two finger-patterned electrodes are vertically separated by employing a multi-layer thin film dielectric of a para-/ferro-/para-electrics without spacing between electrodes. The proposed tunable capacitor was fabricated on a quartz wafer and its characteristics are analyzed in terms of effective capacitance and tunability with a function of applied voltages, compared to the conventional interdigital capacitor (IDC). At 8V and 2 GHz, the proposed tunable capacitor shows the tunability of 18 % that is 10.3 % higher than that of the compared one.