• Nuclear Engineering and Technology
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• v.49 no.2
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• pp.313-326
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• 2017

The systematic management of plant risk is crucial for enhancing the safety of nuclear power plants and for designing new nuclear power plants. Accident sequence precursor (ASP) analysis may be able to provide risk significance of operational experience by using probabilistic risk assessment to evaluate an operational event quantitatively in terms of its impact on core damage. In this study, an ASP methodology for two operation mode, full power and low power/shutdown operation, has been developed and applied to significant accident precursors that may occur during the operation of nuclear power plants. Two operational events, loss of feedwater and steam generator tube rupture, are identified as ASPs. Therefore, the ASP methodology developed in this study may contribute to identifying plant risk significance as well as to enhancing the safety of nuclear power plants by applying this methodology systematically.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.549-551
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• 2005

Bidirectional DC/DC converters allows transfer of power between two dc sources, in either direction. Due to their ability to reverse the direction of flow of power, they are being increasingly used in many applications such as battery charger/dischargers, dc uninterruptible power supplies, electrical vehicle motor drives, aerospace power systems, telecom power supplies, etc. This paper proposes a new bidirectional Sepic/zeta converter. It has low swicthing loss and low conduction loss due to auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of positive and buck/boost-like DC voltage transfer function(M=D/1-D), the proposed converter is very desirable for use in distributed power system . The proposed converter also has both transformerless version and transformer one.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.157-163
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• 2014

This paper proposes a two-stage step-down buck and a tapped-inductor boost cascaded converter for high efficiency photovoltaic micro-inverter applications. The proposed inverter is a new structure to inject a rectified sinusoidal current into a low-frequency switching inverter for single-phase grid with unity power factor. To build a rectified-waveform of the output current. the converter employs both of a high efficiency step-up and a step-down converter in cascade. In step-down mode, tapped inductor(TI) boost converter stops and the buck converter operates alone. In boost mode, the TI converter operates with the halt of buck operation. The converter provides a rectified current to low frequency inverter, then the inverter converts the current into a unity power-factor sinusoidal waveform. By applying a TI, the converter can decrease the turn-on ratios of the main switch in TI boost converter even with an extreme step-up operation. The performance validation of the proposed design is confirmed by an experimental results of a 120W hardware prototype.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.345-348
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• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• Journal of Power Electronics
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• v.13 no.4
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• pp.507-515
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• 2013

This paper presents an isolated bidirectional dc/dc converter based on primary parallel isolated boost converter (PPIBC). This topology is an efficient solution in low voltage high power applications due to its ability to handle high currents in the low voltage side. In this paper, the converter has been modeled using non-ideal components and operated without any additional circuitry for startup using a digital soft-start procedure. Simulated and measured loop gains have been compared for the validity of the model. On-the-fly current direction change has been achieved with a prototype interconnecting two battery banks. A second prototype has been constructed and tested for supercapacitor operation in constant power charge mode.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.93-99
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• 2002

The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• ETRI Journal
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• v.16 no.4
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.49-54
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• 1997

One of the drawbacks of using diode-bridge rectifiers in the unity interface, is the line-current harmonic distortion caused by the nonlinear nature of the rectifier operation. So, a PWM converter for the power factor correction is analysed for unity power factor as well as low cost design, which enable to meet the limits of international standards.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.249-252
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• 2001

A large number of soft switching topologies included a resonant circuit have been proposed. But these circuits increase number of switch in circuit and complicate sequence of switching operation. In this Paper, the authors propose power conversion system, DC-AC inverter of high efficiency and high power factor with soft switching mode by partial resonant method. The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in partial resonant circuit makes charging energy regenerated at input power source for resonant operation.