• Title/Summary/Keyword: Low Power Devices

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A study on performance of the wireless of display devices using Piconet of the Bluetooth (블루투스 피코넷을 이용한 디스플레이 장치의 무선화)

  • Kang Tai-Kyu;Kim Kwang-Sun;Kim Chul-Hwan;Lee Key-Seo
    • Proceedings of the KSR Conference
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    • 2003.05a
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    • pp.480-486
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    • 2003
  • This paper proposes the connection without cables among display devices in a train using piconet of the Bluetooth. Nowadays, each train has a number of the display devices that are connected with many cables to lead the passengers, so it has the waste of resource and factor of fault. This paper proposes the improvement schemes of those problems in a train using piconet of the bluetooth with low cost, low power, and high security.

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Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

  • Jang, Soohyun;Lee, Seongjoo;Jung, Yunho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.255-266
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    • 2015
  • In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

A MedRadio-Band Low Power Low Noise Amplifier for Medical Devices (의료기기용 MedRadio 대역 저전력 저잡음 증폭기)

  • Kim, Taejong;Kwon, Kuduck
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.9
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    • pp.62-66
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    • 2016
  • This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

A novel approach for designing of variability aware low-power logic gates

  • Sharma, Vijay Kumar
    • ETRI Journal
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    • v.44 no.3
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    • pp.491-503
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    • 2022
  • Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

802.11 practical improvements using low power technology

  • Bhargava, Vishal;Raghava, N.S.
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.16 no.5
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    • pp.1735-1754
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    • 2022
  • The reliability and performance of WiFi need optimization because of the rising number of WiFi users day by day. A highlighted point is saving power while transmitting and receiving packets using WiFi devices. Wake-on-Wlan (WoW) is also implemented to improve energy consumption, but it also needs betterment. This paper will introduce universal ideas to transmit and receive packets using low-power technology like Bluetooth or BLE (Bluetooth low energy). While looking for power-saving ways in this research, WiFi connection and maintenance also take care using lesser power-consuming technology. Identifying different use-cases where low power technology can help save energy and maintain 802.11 connection is part of the research. In addition, the proposed method discuss energy saving with unicast and broadcast/multicast data. Calculation of power-saving and comparison with standalone WiFi usage clearly shows the effectiveness of the proposed method.

Switching Transient Analysis and Design of a Low Inductive Laminated Bus Bar for a T-type Converter

  • Wang, Quandong;Chang, Tianqing;Li, Fangzheng;Su, Kuifeng;Zhang, Lei
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1256-1267
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    • 2016
  • Distributed stray inductance exerts a significant influence on the turn-off voltages of power switching devices. Therefore, the design of low stray inductance bus bars has become an important part of the design of high-power converters. In this study, we first analyze the operational principle and switching transient of a T-type converter. Then, we obtain the commutation circuit, categorize the stray inductance of the circuit, and study the influence of the different types of stray inductance on the turn-off voltages of switching devices. According to the current distribution of the commutation circuit, as well as the conditions for realizing laminated bus bars, we laminate the bus bar of the converter by integrating the practical structure of a capacitor bank and a power module. As a result, the stray inductance of the bus bar is reduced, and the stray inductance in the commutation circuit of the converter is reduced to more than half. Finally, a 10 kVA experimental prototype of a T-type converter is built to verify the effectiveness of the designed laminated bus bar in restraining the turn-off voltage spike of the switching devices in the converter.

The Dimmable Single-stage Asymmetrical LLC Resonant LED Driver with Low Voltage Stress Across Switching Devices

  • Kim, Seong-Ju;Kim, Young-Seok;Kim, Choon-Taek;Lee, Joon-Min;La, Jae-Du
    • Journal of Electrical Engineering and Technology
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    • v.10 no.5
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    • pp.2031-2039
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    • 2015
  • In the LED lighting industry, the dimming function in the LED lamp is required by demands of many consumers. To drive this LED lighting, various types of power converters have been applied. Among them, an LLC resonant converter could be applied for high power LED lighting because of its high efficiency and high power density, etc. The function of power factor correction (PFC) might be added to it. In this paper, a dimmable single-stage asymmetrical LLC resonant converter is proposed. The proposed converter performs both input-current harmonics reduction and PFC using the discontinuous conduction mode (DCM). Also, the lower voltage stress across switching devices as well as the zero voltage switching (ZVS) in switching devices is realized by the proposed topology. It can reduce cost and has high efficiency of the driver. In addition, the regulation of the output power by variable switching frequency can vary the brightness of a light. In the proposed converter, one of the attractive advantages doesn’t need any extra control circuits for the dimming function. To verify the performance of the proposed converter, simulation and experimental results from a 300W prototype are provided.

Design of Low-Power Media Bus (저전력 미디어 버스 설계)

  • Roh, Chang-Gu;Moon, Byung-In;Lee, Yong-Hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.2
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    • pp.437-444
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    • 2010
  • The audio data have been communicated using analog methods or simple protocols. However, with the advent and improvement of various multimedia functions, many audio devices have been integrated into a mobile handset in which interconnection lines are very complicated. Conventional point-to-point connections such as $I^2S$ and PCM demand more power consumption whenever more devices are attached. In this paper, we design a common bus digital audio interface that communicates with only two wires and employs the clock gear method to reduce bus power consumption. The comparison results show that the proposed common bus connection can reduce more than 30% of power consumption as compared with point-to-point connection if more than three devices are connected.

A Study on Improvement of Low-power Memory Architecture in IoT/edge Computing (IoT/에지 컴퓨팅에서 저전력 메모리 아키텍처의 개선 연구)

  • Cho, Doosan
    • Journal of the Korean Society of Industry Convergence
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    • v.24 no.1
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    • pp.69-77
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    • 2021
  • The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

Photoluminescence Characterization of Vertically Coupled Low Density InGaAs Quantum Dots for the application to Quantum Information Processing Devices

  • Ha, S.-K.;Song, J.D.
    • Applied Science and Convergence Technology
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    • v.24 no.6
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    • pp.245-249
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    • 2015
  • Vertically coupled low density InGaAs quantum dots (QDs) buried in GaAs matrix were grown with migration enhanced molecular beam epitaxy method as a candidate for quantum information processing devices. We performed excitation power-dependent photoluminescence measurements at cryogenic temperature to analyze the effects of vertical coupling according to the variation in thickness of spacer layer. The more intense coupling effects were observed with the thinner spacer layer, which modified emission properties of QDs significantly. The low surface density of QDs was observed by atomic force microscopy, and scanning transmission electron microscopy verified the successful vertical coupling between low density QDs.