• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• International journal of advanced smart convergence
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• v.9 no.1
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.183-186
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• 1999

The Ultra-miniature and low phase noise Colpitts VCO of 0.06㏄ in size has been developed using the high Q resonator and phase compensation technique. This type is one transistor VCO without a buffer. To design and simulate the VCO accurately, nolinear model parameters of a bipolar transistor are extracted using the measured I-V data and S parameters based on the Gummel-Poon model. Design and simulation have been done by Serenade 7.5 design tool using the extracted nonlinear model parameters. The wideband VCO has been designed using two varactor diodes and open loop gain compensation technique to improve the operating frequency range. The ultra-miniature VCO has shown the phase noise of -91㏈c/Hz at 10KHz offset and output power of -3㏈m The wideband VCO has shown the tuning frequency bandwidth of 150MHz phase noise of -95㏈c/Hz at 10KHz offset and output power of 5㏈m.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1683-1689
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• 1999

We have implemented Frequency bandwidth expander with frequency upconverting by VCO drift canceller and comb generator. Te output of the low frequency synthesizer which the output frequency is 220~280MHz(Resolution : 5MHz) is expanded to 1660~2140MHz by this system. The phase noise of this system only depends on the phase noise of comb generator and low frequency synthesizer. The phase noise of VCO don’t influence at the frequency expander because the drift of VCO cancel out. When we control the output of VCO, the output frequency of this system is varied by 60MHz x N as filter banker. The switching time and the spurious of the frequency expander is below 3usec, -55dBc respectively. This system easily expands bandwidth additively by expanding the output bandwidth of the VCO. We can apply the frequency expander to very wide band microwave synthesizer which has fast switching time.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.25-31
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• 2009

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.413-414
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• 2008

A 2.4 GHz low phase noise fully integrated LC voltage-controlled oscillator (VCO) in $0.18\;{\mu}m$ CMOS technology is presented in this paper. The VCO is optimized based on phase noise reduction. The design of the VCO uses differential varactors which are adopted for symmetry of the circuit, and consider AM-PM conversion due to a cross-coupled pair. The VCO is designed to draw 3 mA from 1.8 V supply voltage. Simulated phase noise is -137.3 dBc/Hz at 3 MHz offset. The tuning range is found to be 300 MHz range from 2.3 GHz to 2.6 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.376-379
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• 2008

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.56-60
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• 2009

In this paper, a novel voltage controlled oscillator (VCO) has been presented by using the microstrip square multiple spiral resonator for reducing the phase noise of VCO. The microstrip multiple square resonator has the large coupling coefficient value, which makes a high Q value, and has reduced phase noise of VCO. The VCO with 1.8 V power supply has phase noise of -115.0~-117.34 dBc/Hz @100 kHz in the tuning range, 8.935~9.4 GHz. When it has been compared with microstrip square multiple spiral resonator and coventional spiral resonator, the reduced Q value has been -32.7 dB and -57.6 dB respectively. This low phase noise VCO could ve available to a VCO in X-band.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.