• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.3-7
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• 2017

Holographic data storage system (HDSS) features short access times, high storage capacities, and fast transfer rates, since the data is recorded and read not by lines but by pages within a volume of holographic material. Burst error caused by physical impact on the high density storage system becomes very longer than that of conventional storage systems. This paper proposes an LDPC product code using two LDPC code to resolve burst error. When a total code rate is similar, the performance of two LDPC code having high code rate is better than that of one LDPC code having low code rate. Also, with error factors of two-dimensional intersysbol interference and misalignment, the proposed scheme can improve the performance in holographic data storage system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.3
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• pp.51-56
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• 2005

To improve the BER of OFDM on a fading channel, a low-density parity check coded OFDM system is proposed in this paper. LDPC codes are decoded with Sum-Product or Belief Propagation Algorithm known by probability propagation algorithm. When LDPC codes are applied to OFDM system, the BER performance is dependant on the iteration number of decoding. To improve the spectral efficiency, multi-level modulations are used in mobile communication system. But, It is not clear how to decode LDPC code used in OFDM with multi-level modulations. In the paper, a decoding algorithm is described for LDPC coded OFDM with MPSK. When use the proposed decoding algorithm, we get the good BER for AWGN and a Fading Channel. Simulation results show that the proposed decoding algorithm is confirmed LDPC coded OFDM with MPSK.

• ETRI Journal
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• v.45 no.1
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• pp.7-17
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• 2023

The error-rate floor of low-density parity-check (LDPC) codes is attributed to the trapping sets of their Tanner graphs. Among them, fully absorbing sets dominantly affect the error-rate performance, especially for short blocklengths. Efficient methods to identify the dominant trapping sets of LDPC codes were thoroughly researched as exhaustively searching them is NP-hard. However, the existing methods are ineffective for Raptor-like LDPC codes, which have many types of trapping sets. An effective method to identify dominant fully absorbing sets of Raptor-like LDPC codes is proposed. The search space of the proposed algorithm is optimized into the Tanner subgraphs of the codes to afford time-efficiency and search-effectiveness. For 5G New Radio (NR) base graph (BG) 2 LDPC codes for short blocklengths, the proposed algorithm finds more dominant fully absorbing sets within one seventh of the computation time of the existing search algorithm, and its search-effectiveness is verified using importance sampling. The proposed method is also applied to 5G NR BG1 LDPC code and Advanced Television Systems Committee 3.0 type A LDPC code for large blocklengths.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.51-59
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• 2004

We design multilevel coding(MLC) with a semi bit-interleaved coded modulation(BICM) scheme based on low density parity check(LDPC) codes. Different from traditional designs, we joint the MLC and BICM together by using the Gray mapping, which can transmit the multimedia data over several equivalent channels with different code rates. To get a good performance from signal-to-noise ratio(SNR) very close to the capacity of the additive white Gaussian noise(AWGN) channel, random regular LDPC code and a simple semi-algebra LDPC(SA-LDPC) code are discussed in MLC with parallel independent decoding(PID). Finally, the numerical results demonstrate that the proposed scheme could achieve both power and bandwidth efficiency for multimedia communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2791-2797
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• 2010

In recent years, the goal of providing high speed wireless data services has generated a great amount of interest among the research community. Several researchers have shown that the capacity of the system, in the presence of flat Rayleigh fading, improves significantly with the use of combined MIMO and LDPC. To feed the soft values to LDPC decoder, the soft values must be calculated from multiple transmitter and receiver antennas in Rayleigh fading channel. It requires high computational complexity to get the soft symbols by increasing number of transmitter and receiver antennas. Therefore, this thesis proposed on effective algorithm for calculation of soft values from multiple antennas based on LLR. As result, This thesis shows that maximum 61% of computational complexity is reduced with a little loss of performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.965-972
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• 2005

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen for second generation digital video broadcasting standard, are required a large number of computation due to large size of coded block and iteration. Therefore, we presented two kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algerian. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and computational complexity of early detected method is about $50\%$ offs in case of check node update, $99\%$ offs in case of check node update compared to conventional scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Information and Communications Magazine
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• v.29 no.8
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• pp.26-33
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• 2012

차세대 통신 시스템에서는 고속 데이터 전송을 위해 다수의 송신자와 수신자가 네트워크를 구성하여 정보를 주고 받는 다자간 협력 통신을 가정한다. 이러한 상황에 적합한 오류 정정 부호로 이미 탁월한 오류 정정 능력을 검증 받은 저밀도 패리티 체크 (low-density parity-check, LDPC)부호, 이진 입력 이산 비기억 (discrete memoryless) 채널에서 무한한 길이에 대하여 채널 용량 (channel capacity)을 달성하는 것으로 알려진 극 부호 (polar code), 아직은 많이 개발되지 않았지만 보다 높은 전송률을 달성할 수 있는 다중점 (multiple point) 채널에서의 새로운 부호 등이 거론될 수 있다. 본고에서는 이러한 차세대 통신 시스템을 위한 오류 정정 부호들에 대해서 기본 이론과 최근 연구 동향, 그리고 향후 연구 방향 등을 소개하도록 한다.